A Practical Example to Understand Pipeline A/D Converters Performance Using Software Tools

Pipeline A/D converters (ADC) are widely used when a high frequency analog signal is sampled. Nevertheless the architecture and operation of this kind of ADC is limited to the domain of microelectronics experts due to their integration in complex mixed-signal IC. Therefore two main problems emerge when a deep study and analysis of the pipeline converters are carried out. The first is related to their internal structure and operating mode, for example the synchronization between the different concurrent stages is a topic of special importance. At the same time, pipeline ADC are difficult to simulate with the CAD tools commonly used by designers of electronic circuits. The second inconvenience is derived from the difficulty of obtaining a dynamic characterization of this architecture. This paper proposes a simple methodology facilitating the understanding of this kind of ADC through simulation and testing of a basic pipeline structure including a rule for clocking the parallel stages. As an example, a 5-bit pipeline ADC is designed and simulated using Oread Pspice and signal-to-noise ratio and distortion (SINAD), the total harmonic distortion (THD) and effective number of bits (ENOB) parameters are obtained from Matlab scripts

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