Circuit simulation algorithms on a distributed memory multiprocessor system

Shared memory multiprocessors have failed to achieve large speedups because of the processor to memory bottleneck, which gets worse as more processors are used. The authors match a distributed memory architecture to the problem to overcome the processor to memory bottleneck. A study is made of parallel source row and target row directed matrix factorization algorithms where the operations are precompiled at the row level. The authors' contribution is in the formulation and analysis of these factorization algorithms for a distributed memory architecture. The authors evaluate the effectiveness of their approach for processor utilization, memory accesses and communication costs for large matrices corresponding to real VLSI circuits. It is shown quantitatively, using the above metrics, that the source row factorization scheme is the most effective.<<ETX>>