Modeling and characterization of substrate resistance for deep submicron ESD protection devices

As device dimensions continue to shrink, higher current densities and lower voltage tolerances make ESD, or Electrostatic Discharge, an increasingly important issue to guard against for ensuring reliability. Industry data show that one-third of all customer returns are due to ESD. IC chips are protected against ESD by on-chip protection circuits, which are connected between the I/O pads and the internal circuitry. The protection circuit, which consists of protection devices, is designed to rapidly discharge high current in an ESD event. Typically, the design of ESD protection circuits is an empirical approach. Several candidate circuits are fabricated, characterized, and evaluated for key physical and performance parameters using known testing techniques. Different combinations of device geometries and process technologies are evaluated until a suitable circuit with the desired characteristics is found. This resource intensive design approach clearly motivates a simulation based solution which enables quicker turnaround as well as obvious cost-savings in materials and resources.

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