Parallel test method for NoC-based SoCs
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[1] Quoc-Tai Duong,et al. High dynamic range power regulator design for UHF band near-field passive RFID tag chips , 2009, 2009 International SoC Design Conference (ISOCC).
[2] Xu Yang,et al. NISAR: An AXI compliant on-chip NI architecture offering transaction reordering processing , 2007, 2007 7th International Conference on ASIC.
[3] Érika F. Cota,et al. Power-aware test scheduling in network-on-chip using variable-rate on-chip clocking , 2005, 23rd IEEE VLSI Test Symposium (VTS'05).
[4] Jin HoAhn,et al. Test Scheduling of NoC-Based SoCs Using Multiple Test Clocks , 2006 .
[5] Sudhakar Yalamanchili,et al. Interconnection Networks: An Engineering Approach , 2002 .
[6] Kees Goossens,et al. AEthereal network on chip: concepts, architectures, and implementations , 2005, IEEE Design & Test of Computers.
[7] Manfred Glesner,et al. Multicast Parallel Pipeline Router Architecture for Network-on-Chip , 2008, 2008 Design, Automation and Test in Europe.
[8] Erik Jan Marinissen,et al. A set of benchmarks for modular testing of SOCs , 2002, Proceedings. International Test Conference.
[9] Erik Jan Marinissen,et al. On using rectangle packing for SOC wrapper/TAM co-optimization , 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).
[10] Sungho Kang,et al. NoC-Based SoC Test Scheduling Using Ant Colony Optimization , 2008 .