Modeling of chip-package-PCB hierarchical power distribution network based on segmentation method

In this paper, a new modeling method for fast estimation of impedance profile in system-level PDN containing not only chip, package and PCB-level PDNs but also various interconnections such as via, ball and bond-wire is proposed. The basic modeling method is segmentation method and FDTD based EM solver and a series of analytic modeling methods such as resonant cavity model and lumped circuit model are used. The proposed modeling method is successfully verified by measurement up to 20 GHz in frequency domain.