Improving Circuit Robustness with Cost-Effective Soft-Error-Tolerant Sequential Elements

Soft errors induced by alpha particles and cosmic radiation have become a highly challenging problem in the design of UDSM or nanoscale circuits, making the incorporation of circuit hardening techniques essential. In this paper, a design technique for soft-error-tolerant sequential elements is presented to improve circuit robustness. The proposed technique exploits time and space redundancy using an elaborate flip-flop structure, and provides complete soft error immunity for both the transient faults generated in the combinatorial logic and the particle strikes inside the flip- flops. The proposed technique is developed to be compatible with current digital design technology, thus having minimal impact on design flow and hardware cost. Simulation results confirm the effectiveness of the proposed technique.

[1]  Abhijit Chatterjee,et al.  Soft-error tolerance analysis and optimization of nanometer circuits , 2005, Design, Automation and Test in Europe.

[2]  G. C. Messenger,et al.  Collection of Charge on Junction Nodes from Ion Tracks , 1982, IEEE Transactions on Nuclear Science.

[3]  L. M. Terman,et al.  The Effect of Alpha-Particle-Induced Soft Errors on Memory Systems with Error Correction , 1979, Fifth European Solid State Circuits Conference - ESSCIRC 79.

[4]  Sujit Dey,et al.  Separate dual-transistor registers: a circuit solution for on-line testing of transient error in UDMC-IC , 2003, 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003..

[5]  Yu Cao,et al.  New generation of predictive technology model for sub-45nm design exploration , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

[6]  Kartik Mohanram,et al.  Design optimization for robustness to single-event upsets , 2006, 24th IEEE VLSI Test Symposium.

[7]  Michael Nicolaidis.  Time redundancy based soft-error tolerance to rescue nanometer technologies , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

[8]  Sujit Dey,et al.  Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[9]  Quming Zhou,et al.  Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[10]  A. Alvandpour,et al.  A 3.5GHz 32mW 150nm multiphase clock generator for high-performance microprocessors , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[11]  N. Seifert,et al.  Robust system design with built-in soft-error resilience , 2005, Computer.

[12]  Kenneth P. Rodbell,et al.  Single-Event Upsets in Microelectronics: Fundamental Physics and Issues , 2003 .

[13]  P. Eaton,et al.  Soft error rate mitigation techniques for modern microcircuits , 2002, 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320).

[14]  Mohamed I. Elmasry,et al.  Design and optimization of multithreshold CMOS (MTCMOS) circuits , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  Robert Baumann,et al.  Soft errors in advanced computer systems , 2005, IEEE Design & Test of Computers.

[16]  S. Kirkpatrick.  Modeling diffusion and collection of charge from ionizing radiation in silicon devices , 1979, IEEE Transactions on Electron Devices.

[17]  R. H. Dennard,et al.  Alpha-particle-induced soft error rate in VLSI circuits , 1982 .

[18]  Eby G. Friedman,et al.  Buffer sizing for delay uncertainty induced by process variations , 2004, Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004..

[19]  G. R. Srinivasan,et al.  Soft-error Monte Carlo modeling program, SEMM , 1996, IBM J. Res. Dev..

[20]  Pinaki Mazumder.  An on-chip ECC circuit for correcting soft errors in DRAMs with trench capacitors , 1992 .