A 12-bit digital-to-time converter (DTC) with sub-ps-level resolution using current DAC and differential switch for time-to-digital converter (TDC)

This paper describes a digital-to-time converter (DTC) architecture that can be used as interpolator in a time-to-digital converter (TDC). The new architecture of the DTC achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range. The propagation delay adjustment is implemented by digitally controlling both the unit load capacitors and the discharge current of the load capacitance using current DAC and differential current switch. The proposed DTC achieves 610 fs resolution and ~2.5 ns dynamic range. The total simulated power consumption is 25.53 mW with 8 MHz conversion rate with 3 V supply. The design was simulated using a 0.35 μm CMOS process.

[1]  A. Mantyniemi,et al.  An integrated 9-channel time digitizer with 30 ps resolution , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[2]  Timo Rahkonen,et al.  The use of stabilized CMOS delay lines for the digitization of short time intervals , 1993 .

[3]  Stephan Henzler,et al.  A Local Passive Time Interpolation Concept for Variation-Tolerant High-Resolution Time-to-Digital Conversion , 2008, IEEE Journal of Solid-State Circuits.

[4]  R. van de Grift,et al.  An 8-bit video ADC incorporating folding and interpolation techniques , 1987 .

[5]  D.J. Allstot.  A precision variable-supply CMOS comparator , 1982, IEEE Journal of Solid-State Circuits.

[6]  Phillip E Allen,et al.  CMOS Analog Circuit Design , 1987 .

[7]  R.B. Staszewski,et al.  All-digital phase-domain TX frequency synthesizer for Bluetooth radios in 0.13/spl mu/m CMOS , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[8]  A.A. Abidi,et al.  A 9 b, 1.25 ps Resolution Coarse–Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue , 2008, IEEE Journal of Solid-State Circuits.

[9]  Gordon W. Roberts,et al.  A jitter characterization system using a component-invariant Vernier delay line , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  Juha Kostamovaara,et al.  A 12-bit digital-to-time converter (DTC) for time-to-digital converter (TDC) and other time domain signal processing applications , 2010, NORCHIP 2010.

[11]  M. Mota,et al.  A high-resolution time interpolator based on a delay locked loop and an RC delay line , 1999, IEEE J. Solid State Circuits.

[12]  Timo Rahkonen,et al.  A CMOS Time-to-Digital Converter (TDC) Based On a Cyclic Time Domain Successive Approximation Interpolation Method , 2009, IEEE Journal of Solid-State Circuits.

[13]  Juha Kostamovaara,et al.  Cyclic time domain successive approximation time-to-digital converter (TDC) with sub-ps-level resolution , 2011, 2011 IEEE International Instrumentation and Measurement Technology Conference.

[14]  T. Sato,et al.  A 1 GHz portable digital delay-locked loop with infinite phase capture ranges , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[15]  Jochen Rivoir.  Fully-Digital Time-To-Digital Converter for ATE with Autonomous Calibration , 2006, 2006 IEEE International Test Conference.