Low Cost C-Testable Finite Field Multiplier Architectures

Design for Test (DFT) techniques attempt to improve access to the internal state of the crypto hardware either by improving control of internal nodes from the primary inputs or by improving observation capability of values on internal nodes at the primary outputs or both. Scan-based test is a powerful Design-For-Testability (DFT) technique.

[1]  Dhiraj K. Pradhan,et al.  Easily Testable Implementation for Bit Parallel Multipliers in GF (2m) , 2006, 2006 IEEE International High Level Design Validation and Test Workshop.

[2]  Hideo Fujiwara.  On Closedness and Test Complexity of Logic Circuits , 1981, IEEE Transactions on Computers.

[3]  Dhiraj K. Pradhan,et al.  A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression , 1991, IEEE Trans. Computers.

[4]  Dhiraj K. Pradhan,et al.  Aliasing Probability for Multiple Input Signature Analyzer , 1990, IEEE Trans. Computers.

[5]  Rodham E. Tulloss,et al.  The Test Access Port and Boundary Scan Architecture , 1990 .

[6]  Tsutomu Sasao.  Easily Testable Realizations for Generalized Reed-Muller Expressions , 1997, IEEE Trans. Computers.

[7]  Ingrid Verbauwhede,et al.  A VLSI design flow for secure side-channel attack resistant ICs , 2005, Design, Automation and Test in Europe.

[8]  Hafizur Rahaman,et al.  Easily testable realization of GRM and ESOP networks for detecting stuck-at and bridging faults , 2004, 17th International Conference on VLSI Design. Proceedings..

[9]  Ramesh Karri,et al.  Scan based side channel attack on dedicated hardware implementations of Data Encryption Standard , 2004 .

[10]  Michel Renovell,et al.  Scan Design and Secure Chip , 2004, IOLTS.

[11]  Hafizur Rahaman,et al.  Testable design of GRM network with EXOR-tree for detecting stuck-at and bridging faults , 2004 .

[12]  Srivaths Ravi,et al.  Tamper resistance mechanisms for secure embedded systems , 2004, 17th International Conference on VLSI Design. Proceedings..

[13]  Ramesh Karri,et al.  Secure scan: a design-for-test architecture for crypto chips , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[14]  Srivaths Ravi,et al.  Security as a new dimension in embedded system design , 2004, Proceedings. 41st Design Automation Conference, 2004..

[15]  Don Douglas Josephson,et al.  Debug methodology for the McKinley processor , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[16]  Mark Mohammad Tehranipoor,et al.  Securing Scan Design Using Lock and Key Technique , 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).