Architecture and Implementation of a First-Generation Iterative Detection Read Channel

This paper explores the architecture of a first-generation iterative detection read channel solution that delivers up to an 8% increase in drive capacity compared to previous generation electronics. Using low density parity check (LDPC) coding, detected data is continually improved by a detection structure that implements multiple iterations through a set of soft-input soft-output (SISO) and message-passing (MP) blocks. A specially constructed LDPC code is used to optimize performance in the presence of inter-symbol interference (ISI). Also, Reed-Solomon error correction coding (ECC) is retained for optimal data integrity. A 65 nm technology is used in the implementation of this design.

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