Key parameters of BiMOS ESD protection device for UTBB FDSOI advanced technology

We investigate the impact of carrier mobility on the performance of a novel Bipolar MOS (BiMOS) device fabricated in Ultra-Thin Body & BOX (UTBB) FDSOI technology. BiMOS transistor combines bipolar and MOS mechanisms that are trigerred by front-gate, back-gate and body biasing. The device response was studied under Average Current Slope (ACS) stress. The mobility value, which depends on channel material and ground-plane implants, primarily affects the breakdown voltage and the device self-heating.

[1]  J. Mazurier,et al.  14nm FDSOI technology for high speed and energy efficient applications , 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

[2]  S. Cristoloveanu,et al.  BIMOS transistor in thin silicon film and new solutions for ESD protection in FDSOI UTBB CMOS technology , 2015, EUROSOI-ULIS 2015: 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon.

[3]  Stephane Monfray,et al.  Improved ESD protection in advanced FDSOI by using hybrid SOI/bulk Co-integration , 2010, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2010.

[4]  Impact of back plane on the carrier mobility in 28nm UTBB FDSOI devices, for ESD applications , 2015, EUROSOI-ULIS 2015: 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon.

[5]  P.K. Ko,et al.  Bipolar-FET hybrid-mode operation of quarter-micrometer SOI MOSFETs (MESFETs read MOSFETs) , 1993, IEEE Electron Device Letters.

[6]  Sorin Cristoloveanu,et al.  Preliminary 3D TCAD electro-thermal simulations of BIMOS transistor in thin silicon film for ESD protection in FDSOI UTBB CMOS technology , 2015, 2015 International Conference on IC Design & Technology (ICICDT).