The Impact of Cache Organization in Optimizing Microprocessor Power Consumption
暂无分享,去创建一个
[1] Burton M. Leary,et al. A 200 MHz 64 b dual-issue CMOS microprocessor , 1992, 1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
[2] Mohamed I. Elmasry,et al. Design and optimization of multithreshold CMOS (MTCMOS) circuits , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[3] Todd M. Austin,et al. The SimpleScalar tool set, version 2.0 , 1997, CARN.
[4] Soha Hassoun,et al. A 200-MHz 64-bit Dual-Issue CMOS Microprocessor , 1992, Digit. Tech. J..
[5] Niraj K. Jha,et al. Leakage power analysis and reduction during behavioral synthesis , 2002, Proceedings 2000 International Conference on Computer Design.
[6] Richard T. Witek,et al. A 160 MHz 32 b 0.5 W CMOS RISC microprocessor , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.