High-frequency SiGe:C HBTs with elevated extrinsic base regions

Abstract This paper reports on the transistor design of high-speed SiGe HBTs with low parasitic resistances and capacitances. Elevated extrinsic base regions and a low-resistance collector design were integrated in a SiGe:C BiCMOS technology to simultaneously minimize base and collector resistances and base-collector capacitance. This technology features CML ring oscillator delays of 3.6 ps per stage for HBTs with f T / f max values of 190/243 GHz and a BV CEO of 1.9 V.

[1]  S. Jeng,et al.  Self-aligned SiGe NPN transistors with 285 GHz f/sub MAX/ and 207 GHz f/sub T/ in a manufacturable technology , 2002, IEEE Electron Device Letters.

[2]  D. Knoll,et al.  Novel collector design for high-speed SiGe:C HBTs , 2002, Digest. International Electron Devices Meeting,.

[3]  B. Jagannathan,et al.  3.9 ps SiGe HBT ECL ring oscillator and transistor design for minimum gate delay , 2003, IEEE Electron Device Letters.

[4]  D. Knoll,et al.  SiGe:C BiCMOS technology with 3.6 ps gate delay , 2003, IEEE International Electron Devices Meeting 2003.

[5]  M. Wurzer,et al.  SiGe bipolar technology with 3.9 ps gate delay , 2003, 2003 Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting (IEEE Cat. No.03CH37440).

[6]  Johannes M. C. Stork.  Bipolar transistor scaling for minimum switching delay and energy dissipation , 1988, Technical Digest., International Electron Devices Meeting.