CASPER — Configurable design space exploration of programmable architectures for machine learning using beyond moore devices
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[1] Yu Ting Chen,et al. A Survey and Evaluation of FPGA High-Level Synthesis Tools , 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[2] Péter Szolgay,et al. Configurable multilayer CNN-UM emulator on FPGA , 2003 .
[3] Y. Rosenwaks,et al. Dynamic and Power Performance of Multiple State Electrostatically Formed Nanowire Transistors , 2017, IEEE Transactions on Electron Devices.
[4] Eriko Nurvitadhi,et al. Accelerating recurrent neural networks in analytics servers: Comparison of FPGA, CPU, GPU, and ASIC , 2016, 2016 26th International Conference on Field Programmable Logic and Applications (FPL).
[5] Vladimir Stojanovic,et al. Design Requirements for a Spintronic MTJ Logic Device for Pipelined Logic Applications , 2016, IEEE Transactions on Electron Devices.