Testing interconnects: a pin adjacency approach

This paper looks at a new fault model used for shorts between nets on a PCB, the pin-adjacency fault model, and the implementation of two algorithms. The pin-adjacency detection and diagnosis algorithms for detecting and diagnosing these bridging faults. The authors represent the nets and their likelihood to short as a graph, and in conjunction with the new algorithms are able to generate reduced test sets. This represents a huge saving over existing algorithms which assume that any two nets are likely to short, as opposed to the new more realistic pin-adjacency fault model.<<ETX>>