Reconfigurable FIR Filter for Dynamic Variation of Filter Order and Filter Coefficients

Reconfigurable finite impulse response (FIR) filters whose filter coefficients and filter order change dynamically during run-time play an important role in the software defined radio (SDR) systems, multi-channel filters, and digital up/down converters. However, there are not many reports on such reconfigurable designs which can support dynamic variation of filter order and filter coefficients. The purpose of this paper is to provide an architectural solution for the FIR filters to support run-time variation of the filter order and filter coefficients. First, two straightforward designs, namely, (i) single-MAC based design and (ii) full-parallel design are presented. For large variation of the filter order, two designs based on (iii) folded structure and (iv) fast FIR algorithm are presented. Finally, we propose (v) high throughput design which provides significant advantage in terms of hardware and/or time complexities over the other designs. We compare complexities of all the five structures, and provide the synthesis results for verification.

[1]  Abbes Amira,et al.  FPGA Realization of FIR Filters by Efficient and Flexible Systolization Using Distributed Arithmetic , 2008, IEEE Transactions on Signal Processing.

[2]  Miodrag Potkonjak,et al.  Multiple constant multiplications: efficient and versatile framework and algorithms for exploring common subexpression elimination , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  A. Dempster,et al.  Use of minimum-adder multiplier blocks in FIR digital filters , 1995 .

[4]  Gerhard Fettweis,et al.  The digital front-end of software radio terminals , 1999, IEEE Wirel. Commun..

[5]  David V. Anderson,et al.  A Reconfigurable Mixed-Signal VLSI Implementation of Distributed Arithmetic Used for Finite-Impulse Response Filtering , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[6]  Ji-Woong Choi,et al.  A Reconfigurable FIR Filter Architecture to Trade Off Filter Performance for Dynamic Power Consumption , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[7]  Sang Yoon Park,et al.  Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  K. Azadet,et al.  A low power 128-tap digital adaptive equalizer for broadband modems , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[9]  A. Prasad Vinod,et al.  New Reconfigurable Architectures for Implementing FIR Filters With Low Complexity , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Indrajit Chakrabarti,et al.  Reconfigurable Architecture of a RRC Fir Interpolator for Multi-standard Digital Up Converter , 2013, 2013 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum.

[11]  Sang Yoon Park,et al.  Critical-Path Analysis and Low-Complexity Implementation of the LMS Adaptive Algorithm , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

[12]  Liu Ming,et al.  The Multiplexed Structure of Multi-channel FIR Filter and its Resources Evaluation , 2012, 2012 International Conference on Computer Distributed Control and Intelligent Environmental Monitoring.

[13]  Ming-Chih Chen,et al.  Low-Cost FIR Filter Designs Based on Faithfully Rounded Truncated Multiple Constant Multiplication/Accumulation , 2013, IEEE Transactions on Circuits and Systems II: Express Briefs.

[14]  James C. Hoe,et al.  Time-Multiplexed Multiple-Constant Multiplication , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[15]  Tzi-Dar Chiueh,et al.  A Low-Power Digit-Based Reconfigurable FIR Filter , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

[16]  A. Prasad Vinod,et al.  Low complexity flexible filter banks for uniform and non-uniform channelisation in software radios using coefficient decimation , 2011, IET Circuits Devices Syst..

[17]  Chip-Hong Chang,et al.  Low-power differential coefficients-based FIR filters using hardware-optimised multipliers , 2007, IET Circuits Devices Syst..

[18]  Venkatesh Krishnan,et al.  LMS adaptive filters using distributed arithmetic for high throughput , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.