A new digit-serial systolic multiplier for finite fields GF(2/sup m/)

This paper presents a new digit-serial systolic multiplier for finite fields GF(2/sup m/). The hardware requirements of the proposed multiplier are less than those of the existing multiplier of the same class, while maintaining the same cell delay. The proposed multiplier possesses the features of regularity, modularity, and unidirectional data flow. Thus, it is well suited to VLSI implementation. If the proposed digit-serial multiplier chooses the digit size L appropriately, it can meet the throughput requirement of a certain application with minimum hardware.

[1]  Whitfield Diffie,et al.  New Directions in Cryptography , 1976, IEEE Trans. Inf. Theory.

[2]  Sun-Yuan Kung,et al.  On supercomputing with systolic/wavefront array processors , 1984 .

[3]  Peter F. Corbett,et al.  Digit-serial processing techniques , 1990 .

[4]  Chin-Liang Wang,et al.  A novel digit-serial systolic array for modular multiplication , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

[5]  R. Blahut.  Theory and practice of error control codes , 1983 .

[6]  Keshab K. Parhi,et al.  Efficient finite field serial/parallel multiplication , 1996, Proceedings of International Conference on Application Specific Systems, Architectures and Processors: ASAP '96.

[7]  C.-L. Wang,et al.  Digit-serial systolic multiplier for finite fields GF(2m) , 1998 .

[8]  S. Kung,et al.  VLSI Array processors , 1985, IEEE ASSP Magazine.

[9]  Keshab K. Parhi,et al.  Efficient semisystolic architectures for finite-field arithmetic , 1998, IEEE Trans. Very Large Scale Integr. Syst..

[10]  Craig K. Rushforth,et al.  A Cellular-Array Multiplier for GF(2m) , 1971, IEEE Transactions on Computers.

[11]  A. Menezes,et al.  Applications of Finite Fields , 1992 .