New burn-in methodology based on IC attributes, family IC burn-in data, and failure mechanism analysis

This paper describes a new methodology for selecting effective burn-in strategies for integrated circuits (ICs) in automotive applications. The method analyzes failure mechanisms for different IC technologies and utilizes family IC data to determine appropriate burn-in conditions for new ICs. The burn-in effectiveness for metal-oxide-semiconductor (MOS) and bipolar technologies is discussed. Burn-in data is presented to demonstrate that burn-in is no longer a cost effective screening process for bipolar ICs and some MOS ICs, but it is still needed for MOS ICs with large die sizes and complex processing technologies. Data also reveals that burn-in is primarily useful for detecting wafer processing defects rather than packaging defects. To select family ICs, a method based on IC attributes is described. Practical guidelines on how to use family IC data and acceleration factors to reduce burn-in time are also explained.

[1]  J. McPherson,et al.  Acceleration Factors for Thin Gate Oxide Stressing , 1985, 23rd International Reliability Physics Symposium.

[2]  E. A. Amerasekera,et al.  Failure Mechanisms in Semiconductor Devices , 1987 .

[3]  D. Gralian,et al.  Next generation burn-in development , 1994 .

[4]  A. Suyko,et al.  Development of a burn-in time reduction algorithm using the principles of acceleration factors , 1991, 29th Annual Proceedings Reliability Physics 1991.

[5]  J. M. Funyak.  Burn-in requirements, trends and testing procedures on electrical components for a major US automotive manufacturer , 1992, [Proceedings] APEC '92 Seventh Annual Applied Power Electronics Conference and Exposition.

[6]  H.H. Huston,et al.  Burn-in effectiveness-theory and measurement , 1991, 29th Annual Proceedings Reliability Physics 1991.

[7]  C.H. Stapper,et al.  Integrated circuit yield statistics , 1983, Proceedings of the IEEE.

[8]  Barbara Vasquez,et al.  Known-good-die technologies on the horizon , 1994, Proceedings of IEEE VLSI Test Symposium.

[9]  Dragan Pantic.  Benefits of Integrated-Circuit Burn-In to Obtain High Reliability Parts , 1986, IEEE Transactions on Reliability.

[10]  W. Smith,et al.  Does the burn-in of integrated circuits continue to be a meaningful course to pursue , 1988, 38th Electronics Components Conference 1988., Proceedings..

[11]  D. L. Crook.  Evolution of VLSI reliability engineering , 1990 .

[12]  C. Hu,et al.  Reliability issues of MOS and bipolar ICs , 1989, Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[13]  Dwight L. Crook,et al.  Method of Determining Reliability Screens for Time Dependent Dielectric Breakdown , 1979, 17th International Reliability Physics Symposium.