A Review of VLSI Structure for the Implementation of Matrix Multiplication

Matrix multiplication is the kernel operation used in many transform, image processing and digital signal processing application. In this paper, we have studied for parallel-parallel input and single output (PPI-SO), parallel-parallel input and multiple output (PPI-MO) and parallel-parallel fixed input and multiple output (PFI-MO) matrix-matrix multiplication. It is also a well-known fact that the multiplier and adder unit forms an integral part of matrix multiplication. Due to this regard, high speed multiplier and adder become the need of the day. In this paper, we have studied of Vedic mathematics multiplier using compressors.

[1]  Abbes Amira,et al.  Accelerating Matrix Product on Reconfigurable Hardware for Signal Processing , 2001, FPL.

[2]  Jack Belzer,et al.  Encyclopedia of Computer Science and Technology , 2002 .

[3]  D. H. Horrocks,et al.  Overview and design directions for low-power circuits and architectures for digital signal processing , 1995 .

[4]  Peter A. Beerel,et al.  An asynchronous pipeline comparisons with application to DCT matrix-vector multiplication , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[5]  Massoud Pedram,et al.  Design Technologies for Low Power VLSI , 1995 .

[6]  Phillip H. Jones,et al.  An I/O Bandwidth-Sensitive Sparse Matrix-Vector Multiplication Engine on FPGAs , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.

[7]  S. R. Rupanagudi,et al.  Novel high speed vedic mathematics multiplier using compressors , 2013, 2013 International Mutli-Conference on Automation, Computing, Communication, Control and Compressed Sensing (iMac4s).

[8]  Tughrul Arslan,et al.  Digest of IEE Colloquium on Low Power Analogue and Digital VLSI: ASICS, Techniques and Applications , 1995 .

[9]  Keshab K. Parhi,et al.  VLSI digital signal processing systems , 1999 .

[10]  Viktor K. Prasanna,et al.  Energy- and time-efficient matrix multiplication on FPGAs , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[11]  Nitin Meena,et al.  FPGA Design and Implementation of Matrix Multiplication Architecture by PPI-MO Techniques , 2013 .

[12]  Nitin Meena,et al.  Efficient Hardware Design for Implementation ofMatrix Multiplication by using PPI-SO , 2013 .

[13]  Michael J. Flynn,et al.  PAM-Blox: high performance FPGA design for adaptive computing , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).