Area Optimized Hardware Architecture of Piccolo-80 Lightweight Block Cipher

Lightweight cryptography is a field of cryptography where implementation for resource constrained devices are in big demand. Piccolo is an ultra-lightweight block cipher having block size of 64-bit and key size of 80-bit and 128-bit. Compact implementations becomes more important when they can provide sufficient security without compromise in performance. In this paper an efficient architecture for Piccolo-80 cipher have been proposed. This cipher requires extreamely low area in hardware implementation, and hence it is useful in RFID applications. Piccolo with its proposed architecture has been implemented on various platforms of FPGA.The proposed work shows 112% improvement in terms of area and 17.65% better results in terms of efficiency. Different devices of Virtex and Spartan have been used to get the results.

[1]  Simon Heron,et al.  Encryption: Advanced Encryption Standard (AES) , 2009 .

[2]  Kyoji Shibutani,et al.  Piccolo: An Ultra-Lightweight Blockcipher , 2011, CHES.

[3]  Christophe De Cannière,et al.  KATAN and KTANTAN - A Family of Small and Efficient Hardware-Oriented Block Ciphers , 2009, CHES.

[4]  Andrey Bogdanov,et al.  PRESENT: An Ultra-Lightweight Block Cipher , 2007, CHES.

[5]  Bibhudendra Acharya,et al.  A comparative survey on lightweight block ciphers for resource constrained applications , 2019, Int. J. High Perform. Syst. Archit..

[6]  Jason Smith,et al.  The SIMON and SPECK lightweight block ciphers , 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[7]  Bibhudendra Acharya,et al.  A comparative survey on lightweight block ciphers for resource constrained applications , 2019 .

[8]  Guang Gong,et al.  FPGA implementations of the Hummingbird cryptographic algorithm , 2010, 2010 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).

[9]  Bibhudendra Acharya,et al.  Performance optimised architectures of Piccolo block cipher for low resource IoT applications , 2020 .

[10]  Pulkit Singh,et al.  Efficient VLSI Architectures of LILLIPUT Block Cipher for Resource-constrained RFID Devices , 2019, 2019 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT).

[11]  Jens-Peter Kaps,et al.  Lightweight Cryptography for FPGAs , 2009, 2009 International Conference on Reconfigurable Computing and FPGAs.

[12]  Pulkit Singh,et al.  High Throughput Architecture for KLEIN Block Cipher in FPGA , 2019, 2019 9th Annual Information Technology, Electromechanical Engineering and Microelectronics Conference (IEMECON).

[13]  Gandu Ramu,et al.  Performance optimised architectures of Piccolo block cipher for low resource IoT applications , 2020, Int. J. High Perform. Syst. Archit..

[14]  Hui Wang,et al.  QTL: A new ultra-lightweight block cipher , 2016, Microprocess. Microsystems.

[15]  Jens-Peter Kaps,et al.  Chai-Tea, Cryptographic Hardware Implementations of xTEA , 2008, INDOCRYPT.

[16]  Miguel Morales-Sandoval,et al.  Lightweight Hardware Architectures for the Present Cipher in FPGA , 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.

[17]  Jens-Peter Kaps,et al.  Compact FPGA implementation of Camellia , 2009, 2009 International Conference on Field Programmable Logic and Applications.

[18]  Jagdish Patil,et al.  LiCi: A new ultra-lightweight block cipher , 2017, 2017 International Conference on Emerging Trends & Innovation in ICT (ICEI).

[19]  Daesung Kwon,et al.  LEA: A 128-Bit Block Cipher for Fast Encryption on Common Processors , 2013, WISA.

[20]  Miodrag Potkonjak,et al.  Security of IoT systems: Design challenges and opportunities , 2014, 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[21]  Daesung Kwon,et al.  Efficient Hardware Implementation of the Lightweight Block Encryption Algorithm LEA , 2014, Sensors.