Application-specific network-on-chip architecture customization via long-range link insertion

Networks-on-chip (NoCs) represent a promising solution to complex on-chip communication problems. The NoC communication architectures considered so far are based on either completely regular or fully customized topologies. In this paper, we present a methodology to automatically synthesize an architecture where a few application-specific long-range links are inserted on top of a regular mesh network. This way, we can better exploit the benefits of both complete regularity and partial customization. Indeed, our experimental results show that inserting application-specific long-range links significantly increases the critical traffic workload at which the network state transits from a free to a congested regime. This, in turn, results in a significant reduction in the average packet latency and a major improvement in the network achievable throughput.

[1]  Lionel M. Ni,et al.  The Turn Model for Adaptive Routing , 1992, [1992] Proceedings the 19th Annual International Symposium on Computer Architecture.

[2]  Sudhakar Yalamanchili,et al.  Interconnection Networks: An Engineering Approach , 2002 .

[3]  Duncan J. Watts,et al.  Collective dynamics of ‘small-world’ networks , 1998, Nature.

[4]  Anna T. Lawniczak,et al.  Performance of data networks with random links , 1999, ArXiv.

[5]  Alberto L. Sangiovanni-Vincentelli,et al.  Theory of latency-insensitive design , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[7]  L. Benini,et al.  Analysis of power consumption on switch fabrics in network routers , 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

[8]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[9]  M Woolf,et al.  Optimization and phase transitions in a chaotic model of data traffic. , 2002, Physical review. E, Statistical, nonlinear, and soft matter physics.

[10]  Alberto L. Sangiovanni-Vincentelli,et al.  Efficient synthesis of networks on chip , 2003, Proceedings 21st International Conference on Computer Design.

[11]  R. Marculescu,et al.  Exploiting the routing flexibility for energy/performance aware mapping of regular NoC architectures , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[12]  Luca Benini,et al.  ×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip , 2004, DATE.

[13]  Krishnan Srinivasan,et al.  Linear programming based techniques for synthesis of network-on-chip architectures , 2006, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

[14]  L. Benini,et al.  /spl times/pipesCompiler: a tool for instantiating application specific networks on chip , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[15]  Srinivasan Murali,et al.  SUNMAP: a tool for automatic topology selection and generation for NoCs , 2004, Proceedings. 41st Design Automation Conference, 2004..

[16]  Axel Jantsch,et al.  The Nostrum backbone-a communication protocol stack for Networks on Chip , 2004, 17th International Conference on VLSI Design. Proceedings..

[17]  ×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip , 2004 .

[18]  D. Glickenstein,et al.  Small world phenomenon and decentralized search , 2004 .

[19]  Lawrence T. Pileggi,et al.  An interconnect channel design methodology for high performance integrated circuits , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[20]  Kees G. W. Goossens,et al.  A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification , 2005, Design, Automation and Test in Europe.

[21]  Radu Marculescu,et al.  Energy- and performance-driven NoC communication architecture synthesis using a decomposition approach , 2005, Design, Automation and Test in Europe.