BADGR: A practical GHR implementation for TAGE branch predictors

In this work, we explore global history register (GHR) implementations for Tagged Geometric length (TAGE) style branch predictors with speculative updates. We break down the requirements to both update and recover TAGE predictors' history registers during normal operation and after mispeculation, discussing where various designs exhibit large checkpoint and/or operation overheads. To reduce these inefficiencies, we introduce BADGR, a novel GHR design for TAGE predictors that lowers power consumption and chip area over naive checkpointing techniques by 90% and 85%, respectively.

[1]  Kevin Skadron,et al.  Power issues related to branch prediction , 2002, Proceedings Eighth International Symposium on High Performance Computer Architecture.

[2]  André Seznec.  Storage free confidence estimation for the TAGE branch predictor , 2011, 2011 IEEE 17th International Symposium on High Performance Computer Architecture.

[3]  Eric Sprangle,et al.  Increasing processor performance by implementing deeper pipelines , 2002, ISCA.

[4]  Daniel A. Jiménez.  An optimized scaled neural branch predictor , 2011, 2011 IEEE 29th International Conference on Computer Design (ICCD).

[5]  Norman P. Jouppi,et al.  CACTI 5.0 , 2007 .

[6]  Margaret Martonosi,et al.  Runtime Power Monitoring in High-End Processors: Methodology and Empirical Data , 2003, MICRO.

[7]  Hans Vandierendonck,et al.  Speculative return address stack management revisited , 2008, TACO.

[8]  Somayeh Sardashti,et al.  The gem5 simulator , 2011, CARN.

[9]  Dirk Grunwald,et al.  Confidence estimation for speculation control , 1998, ISCA.

[10]  André Seznec.  A 64 Kbytes ISL-TAGE branch predictor , 2011 .

[11]  Yale N. Patt,et al.  Recovery requirements of branch prediction storage structures in the presence of mispredicted-path execution , 2007, International Journal of Parallel Programming.

[12]  Mikko H. Lipasti,et al.  Bias-Free Branch Predictor , 2014, 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture.

[13]  André Seznec,et al.  A new case for the TAGE branch predictor , 2011, 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[14]  Margaret Martonosi,et al.  Improving prediction for procedure returns with return-address-stack repair mechanisms , 1998, Proceedings. 31st Annual ACM/IEEE International Symposium on Microarchitecture.

[15]  Eric Rotenberg,et al.  Assigning confidence to conditional branch predictions , 1996, Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture. MICRO 29.

[16]  James E. Smith,et al.  A first-order superscalar processor model , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..