论文信息 - Structural tests for jitter tolerance in SerDes receivers

Structural tests for jitter tolerance in SerDes receivers

A suite of structural tests is described that uses on-chip under sampling to measure parameters that affect jitter tolerance in a multi-gigabit-per-second (Gbps) receiver. The tests measure high-frequency jitter (RMS value and histogram) in the received signal and in the recovered clock, plus transition-density dependent phase-shift, mean sampling position in the signal eye, sampling clock phase error, and pin-to-pin skew, all with near-picosecond resolution and repeatability, in tens of milliseconds. Hardware results for a 3 Gbps serializer/ deserializer (SerDes) IC are included. The new method is suitable for an unlimited number of channels, it simplifies test hardware, it reduces production test time, and is suitable for any tester. The diagnostic capabilities facilitate improving yield and quality

Aubin Roy | Stephen K. Sunter

[1] Dongwoo Hong,et al. An efficient random jitter measurement technique using fast comparator sampling , 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

[2] J.-F. Cote,et al. An automated, complete, structural test solution for SERDES , 2004 .

[3] J.D.H. Alexander. Clock recovery from random binary signals , 1975 .

[4] T. M. Mak,et al. Elimination of traditional functional testing of interface timings at intel , 2003 .

[5] James E. Jaussi,et al. An 8-Gb/s simultaneous bidirectional link with on-die waveform capture , 2003, IEEE J. Solid State Circuits.

[6] Aubin Roy,et al. On-chip digital jitter measurement, from megahertz to gigahertz , 2004, IEEE Design & Test of Computers.

[7] Hui Wang,et al. Low-power fully integrated 10-Gb/s SONET/SDH transceiver in 0.13-μm CMOS , 2003, IEEE J. Solid State Circuits.