The Validator tool suite: filling the gap between conventional soft- ware-in-the-loop and hardware-in-the-loop simulation environments

Software-In-the-Loop (SIL) and Hardware-In-the-Loop (HIL) simulation environments represent established methods and tools for testing real-time embedded systems before they are deployed in products. Nevertheless, some key features that we regard as crucial for improving the quality of embedded systems are missing in both conventional SIL and HIL approaches. What we have called the Validator, a cutting-edge simulation environment for verification and validation, fills that gap. The Validator offers the advantages of SIL simulations in terms of cost and simulation speed as well as the advantages of HIL simulations in terms of accuracy. The new key feature of the Validator is advanced debugging of embedded systems that deals with timing behavior as if the software would be executed on a target platform. The Validator also offers regression testing at a level of granularity that leads to a solid comparison between several versions of a system, for example, a legacy system and its reengineered or enhanced artefact. The Validator was applied to large industrial legacy systems for simulating the computational part in closed-loop with continuous-time plant models in MATLAB ® /Simulink ® . For that purpose, the Validator allows co-simulation with other simulation tools based on time synchronization protocols. This chapter

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