Design verification for very large digital networks based on concurrent simulation and clock suppression

A methodology is presented for design verification of very large networks based on concurrent simulation and clock suppression. Concurrent case simulation consists of the concurrent injection and simulation of many input bit vectors into a given network model. This permits, relative to normal serial simulation, concurrent simulation of large numbers of cases of good machines at a very high speed. This speed advantage increases with the number of cases. Clock suppression is an auxiliary technique to avoid simulation slowdowns if networks with very large clock fanouts must be simulated. 11 references.