Three-dimensional stacked MOS transistors by localized silicon epitaxial overgrowth

Three-dimensionally integrated silicon-on-insulator MOS transistors built employing localized silicon epitaxy are discussed. Key parameters for the growth of single-crystal silicon over oxidized polysilicon gates to form channel regions for stacked devices were obtained. The interface between the buried oxide and the silicon overgrowth was characterized by C-V measurements, exhibiting interface state densities as low as 2*10/sup 11//eV-cm/sup 2/ at mid-gap. A self-limiting planarization technique to thin the overgrowth to less than 1 mu m to facilitate the implementation of active devices was developed. The quality of the crystalline material and the planarized surface was characterized by means of MOS transistors that exhibited hole mobilities (165 cm/sup 2//V-s) comparable to those of bulk material. Field-effect operation of the buried interface composed of the oxidized polysilicon and the overgrowth was demonstrated. >

[1]  Nobuhiro Endo,et al.  1/4-µm CMOS isolation technique using selective epitaxy , 1987, IEEE Transactions on Electron Devices.

[2]  G. R. Srinivasan.  Autodoping Effects in Silicon Epitaxy , 1980 .

[3]  G. Neudeck,et al.  Oxide degradation during selective epitaxial growth of silicon , 1988 .

[4]  E. F. Steigmeier,et al.  High quality polysilicon by amorphous low pressure chemical vapor deposition , 1983 .

[5]  H.-J. Pfleiderer,et al.  CMOS-Technology - Status, Trends and Applications , 1988, ESSDERC '88: 18th European Solid State Device Research Conference.

[6]  Y. Mikata,et al.  Reduction in Polysilicon Oxide Leakage Current by Annealing prior to Oxidation , 1985 .

[7]  E. Irene,et al.  Silicon Oxidation Studies: Morphological Aspects of the Oxidation of Polycrystalline Silicon , 1980 .

[8]  M. Nakamae,et al.  Novel LSI/SOI wafer fabrication using device layer transfer technique , 1985, 1985 International Electron Devices Meeting.

[9]  G. Rubloff,et al.  Role of oxygen in defect‐related breakdown in thin SiO2 films on Si (100) , 1987 .

[10]  B. Hofflinger,et al.  Stacked CMOS inverter with symmetric device performance , 1989, International Technical Digest on Electron Devices Meeting.

[11]  G. Ghidini,et al.  Reaction of Oxygen with Si(111) and (100): Critical Conditions for the Growth of SiO2 , 1982 .

[12]  T. Sekigawa,et al.  Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate , 1984 .

[13]  H. Beneking,et al.  Submicron highly doped Si layers grown by LPVPE , 1986 .

[14]  G. Neudeck,et al.  Interface characterization of silicon epitaxial lateral growth over existing SiO/sub 2/ for three-dimensional CMOS structures , 1989, IEEE Electron Device Letters.

[15]  S. T. Liu,et al.  Limitations in low‐temperature silicon epitaxy due to water vapor and oxygen in the growth ambient , 1988 .

[16]  R. Mountain,et al.  Vertical single-gate CMOS inverters on laser-processed multilayer substrates , 1981, 1981 International Electron Devices Meeting.

[17]  L. Jastrzebski.  SOI by CVD: Epitaxial Lateral Overgrowth (ELO) process—Review , 1983 .

[18]  J.O. Borland.  Novel device structures by selective epitaxial growth (SEG) , 1987, 1987 International Electron Devices Meeting.

[19]  E. Ganin,et al.  Low temperature silicon epitaxy by hot wall ultrahigh vacuum/low pressure chemical vapor deposition techniques: surface optimization , 1986 .

[20]  H. Shichijo,et al.  Characteristics and Three-Dimensional Integration of MOSFET's in Small-Grain LPCVD Polycrystalline Silicon , 1985, IEEE Journal of Solid-State Circuits.

[21]  Rafael Reif,et al.  Silicon epitaxy at 650–800 °C using low‐pressure chemical vapor deposition both with and without plasma enhancement , 1985 .

[22]  F. Balestra,et al.  Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance , 1987, IEEE Electron Device Letters.

[23]  G. Rubloff,et al.  Defect formation in thermal SiO2 by high‐temperature annealing , 1986 .