Exploiting optical interconnects to eliminate serial bottlenecks

Optical interconnects offer interesting new possibilities because of the potential for scalable broadcast. Unfortunately, most current algorithms using broadcast do not scale well because of the rapid increase in message processing resulting from broadcast, and particularly because of potential uneven distribution of the work. We describe a novel design as an example of how an architecture might exploit broadcast capability not so much to speed up easily parallelized code as to minimize the effects of serial bottlenecks. While compatible with compiler-discovered parallel programs, the architecture appears particularly promising for code that exhibits serial bottlenecks. The architecture appears well suited for future directions of semiconductor and optical technologies.

[1]  James R. Goodman,et al.  Memory Bandwidth Limitations of Future Microprocessors , 1996, 23rd Annual International Symposium on Computer Architecture (ISCA'96).

[2]  John F. Beetem,et al.  The GF11 supercomputer , 1985, ISCA '85.

[3]  Tom Lovett,et al.  STiNG: A CC-NUMA Computer System for the Commercial Marketplace , 1996, 23rd Annual International Symposium on Computer Architecture (ISCA'96).

[4]  Anoop Gupta,et al.  The Stanford Dash multiprocessor , 1992, Computer.

[5]  Ralph Grishman,et al.  The NYU Ultracomputer—Designing an MIMD Shared Memory Parallel Computer , 1983, IEEE Transactions on Computers.

[6]  Richard J. Lipton,et al.  A Massive Memory Machine , 1984, IEEE Transactions on Computers.

[7]  W. Daniel Hillis,et al.  The Network Architecture of the Connection Machine CM-5 , 1996, J. Parallel Distributed Comput..

[8]  A. Gupta,et al.  The Stanford FLASH multiprocessor , 1994, Proceedings of 21 International Symposium on Computer Architecture.

[9]  J. Larus,et al.  Tempest and Typhoon: user-level shared memory , 1994, Proceedings of 21 International Symposium on Computer Architecture.

[10]  Michael J. Flynn,et al.  Some Computer Organizations and Their Effectiveness , 1972, IEEE Transactions on Computers.

[11]  Kevin P. McAuliffe,et al.  The IBM Research Parallel Processor Prototype (RP3): Introduction and Architecture , 1985, ICPP.