Two Dimensional Analytical Modeling Of A Nanoscale Dual Material Gate MOSFETS
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[1] B.C. Paul,et al. Device optimization for digital subthreshold logic operation , 2005, IEEE Transactions on Electron Devices.
[2] Subhasis Haldar,et al. Impact of graded channel (GC) design in fully depleted cylindrical/surrounding gate MOSFET (FD CGT/SGT) for improved short channel immunity and hot carrier reliability , 2007 .
[3] G. V. Reddy,et al. Evidence for suppressed short-channel effects in deep submicron dual-material gate (DMG) partially depleted SOI MOSFETs – A two-dimensional analytical approach , 2004 .
[4] Guruprasad Katti,et al. Unified analytical threshold voltage model for non-uniformly doped dual metal gate fully depleted silicon-on-insulator MOSFETs , 2009 .
[5] M.J. Kumar,et al. Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs , 2004, IEEE Transactions on Electron Devices.
[6] M. J. Kumar,et al. Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review , 2004, IEEE Transactions on Device and Materials Reliability.
[7] Chenming Hu,et al. Dual work function metal gate CMOS technology using metal interdiffusion , 2001, IEEE Electron Device Letters.
[8] James D. Plummer,et al. Material and process limits in silicon VLSI technology , 2001, Proc. IEEE.
[9] D. Monroe,et al. Analytic description of short-channel effects in fully-depleted double-gate and cylindrical, surrounding-gate MOSFETs , 2000, IEEE Electron Device Letters.