Linear sifting of decision diagrams

We propose a new algorithm, called linear sifting, for theoptimization of decision diagrams that combines the efficiency of sifting and the power of linear transformations. We show that the new algorithm is applicable to large examples, and that inmany cases it leads to substantiallymore compact diagrams when compared to simple variablereordering. We show inwhat sense linear transformationscomplement variable reordering, and we discuss applications of the new technique to synthesis and verification.

[1]  Robert K. Brayton,et al.  BDD minimization by truth table permutations , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[2]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[3]  F. Somenzi,et al.  Who are the variables in your neighbourhood , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[4]  Yung-Te Lai,et al.  Edge-valued binary decision diagrams for multi-level hierarchical verification , 1992, DAC '92.

[5]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[6]  Randal E. Bryant,et al.  Efficient implementation of a BDD package , 1991, DAC '90.

[7]  Wolfgang Rosenstiel,et al.  Multilevel logic synthesis based on functional decision diagrams , 1992, [1992] Proceedings The European Conference on Design Automation.

[8]  Fabio Somenzi,et al.  Who are the variables in your neighborhood , 1995, ICCAD.

[9]  Kavita Ravi,et al.  High-density reachability analysis , 1995, ICCAD.

[10]  Paolo Prinetto,et al.  A new model for improving symbolic product machine traversal , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[11]  Christoph Meinel,et al.  Local Encoding Transformations for Optimizing OBDD-Representations of Finite State Machines , 1996, Formal Methods Syst. Des..

[12]  Robert K. Brayton,et al.  Sequential circuit design using synthesis and optimization , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[13]  Masahiro Fujita,et al.  On variable ordering of binary decision diagrams for the application of multi-level logic synthesis , 1991, Proceedings of the European Conference on Design Automation..

[14]  Jochen Bern,et al.  Efficient OBDD-Based Boolean Manipulation in CAD Beyond Current Limits , 1995, 32nd Design Automation Conference.

[15]  F. Brglez,et al.  A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .

[16]  Sarma Sastry,et al.  Edge-valued binary decision for multi-level hierarchical verification , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[17]  Shin-ichi Minato,et al.  Zero-Suppressed BDDs for Set Manipulation in Combinatorial Problems , 1993, 30th ACM/IEEE Design Automation Conference.

[18]  Enrico Macii,et al.  Algorithms for approximate FSM traversal based on state space decomposition , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[19]  Richard Rudell.  Dynamic variable ordering for ordered binary decision diagrams , 1993, ICCAD.

[20]  Edmund M. Clarke,et al.  Model checking and abstraction , 1994, TOPL.

[21]  Robert P. Kurshan,et al.  Computer-Aided Verification of Coordinating Processes: The Automata-Theoretic Approach , 2014 .

[22]  Randal E. Bryant,et al.  Verification of Arithmetic Circuits with Binary Moment Diagrams , 1995, 32nd Design Automation Conference.

[23]  R. Rudell.  Dynamic variable ordering for ordered binary decision diagrams , 1993, ICCAD 1993.

[24]  Enrico Macii,et al.  Algorithms for Approximate FSM Traversal , 1993, 30th ACM/IEEE Design Automation Conference.

[25]  S. Yang,et al.  Logic Synthesis and Optimization Benchmarks User Guide Version 3.0 , 1991 .

[26]  Masatoshi Sekine,et al.  Synthesis by spectral translation using Boolean decision diagrams , 1996, DAC '96.