Performance and power evaluation of a 3D CMOS/nanomaterial reconfigurable architecture

In this paper, we introduce a novel reconfigurable architecture, named 3D nFPGA, which utilizes 3D integration techniques and new nanoscale materials synergistically. The proposed architecture is based on CMOS-nano hybrid techniques that incorporate nanomaterials such as carbon nanotube bundles and nanowire crossbars into CMOS fabrication process. Using unique features of FPGAs and a novel 3D stacking method enabled by the application of nanomaterials, 3D nFPGA obtains a 4.5X footprint reduction compared to traditional CMOS-based 2D FPGAs. With a customized design automation flow, we evaluate the performance and power of 3D nFPGA driven by the 20 largest MCNC benchmarks. Results demonstrate that 3D nFPGA is able to provide a performance gain of 2.6X with a small power overhead comparing to the CMOS 2D FPGA architecture.

[1]  Raphael Rubin,et al.  3D Nanowire-Based Programmable Logic , 2006, 2006 1st International Conference on Nano-Networks and Workshops.

[2]  K. Banerjee,et al.  Carbon nanotube interconnects: implications for performance, power dissipation and thermal management , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[3]  R. Williams,et al.  Nano/CMOS architectures using a field-programmable nanowire interconnect , 2007 .

[4]  Jason Cong,et al.  Power modeling and characteristics of field programmable gate arrays , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Mingjie Lin,et al.  Performance Benefits of Monolithically Stacked 3-D FPGA , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Wei Wang,et al.  Exploring carbon nanotubes and NiSi nanowires as on-chip interconnections , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[7]  Wei Wu,et al.  Fabrication of 5 nm linewidth and 14 nm pitch features by nanoimprint lithography , 2004 .

[8]  Wei Zhang,et al.  NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[9]  André DeHon,et al.  Nanowire-based programmable architectures , 2005, JETC.

[10]  Jian Xu,et al.  Demystifying 3D ICs: the pros and cons of going vertical , 2005, IEEE Design & Test of Computers.

[11]  Jason Cong,et al.  DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs , 2004, ICCAD 2004.

[12]  R. Stanley Williams,et al.  CMOS-like logic in defective, nanoscale crossbars , 2004 .

[13]  Vaughn Betz,et al.  Architecture and CAD for Deep-Submicron FPGAS , 1999, The Springer International Series in Engineering and Computer Science.

[14]  Kaushik Roy,et al.  Modeling of metallic carbon-nanotube interconnects for circuit simulations and a comparison with Cu interconnects for scaled technologies , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[15]  Mark Mohammad Tehranipoor,et al.  A new hybrid FPGA with nanoscale clusters and CMOS routing , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[16]  A. Kawabata,et al.  Carbon nanotube vias for future LSI interconnects , 2004, Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729).

[17]  J. Meindl,et al.  Performance comparison between carbon nanotube and copper interconnects for gigascale integration (GSI) , 2005, IEEE Electron Device Letters.

[18]  D. Strukov,et al.  CMOL FPGA: a reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices , 2005 .

[19]  Arijit Raychowdhury,et al.  Circuit modeling of carbon nanotube interconnects and their performance estimation in VLSI design , 2004, 2004 Abstracts 10th International Workshop on Computational Electronics.

[20]  Jonathan Rose,et al.  The effect of LUT and cluster size on deep-submicron FPGA performance and density , 2004 .

[21]  Seth Copen Goldstein,et al.  NanoFabrics: spatial computing using molecular electronics , 2001, ISCA 2001.

[22]  P. R. Stephan,et al.  SIS : A System for Sequential Circuit Synthesis , 1992 .

[23]  R. Smalley,et al.  Electrical and thermal transport properties of magnetically aligned single wall carbon nanotube films , 2000 .

[24]  J. F. Stoddart,et al.  Nanoscale molecular-switch crossbar circuits , 2003 .

[25]  Kia Bazargan,et al.  Exploring Potential Benefits of 3D FPGA Integration , 2004, FPL.

[26]  Narayanan Vijaykrishnan,et al.  Exploring technology alternatives for nano-scale FPGA interconnects , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[27]  Wei Lu,et al.  Single-crystal metallic nanowires and metal/semiconductor nanowire heterostructures , 2004, Nature.