Scheme for low-power write assist the sram

For low power SRAM write assist program. Secondary memory comprises a memory write voltage supply and a column of SRAM cells controlled during a write operation by the bit line. Further, the auxiliary memory comprises a write write assist unit, which is coupled to the supply voltage and the SRAM column of memory cells and having a detachable wire between the bit line pair of separable conductors on the bit line during a write operation the SRAM supply voltage of the capacitive coupling of the control signal supplied to the column collapsible SRAM cells. Also provided is a method of operating to auxiliary storage.