Compaction of a Functional Broadside Test Set through the Compaction of a Functional Test Sequence without Sequential Fault Simulation

Functional broadside tests avoid overtesting of delay faults by creating functional operation conditions during the clock cycles where they detect delay faults. One of the challenges in the generation of functional broadside tests is test compaction. Existing dynamic compaction approaches for scan tests are not applicable to functional broadside tests, and static compaction approaches are limited in the level of test compaction they can provide. The solution suggested in this paper has two new properties. (1) Instead of attempting to compact functional broadside tests, test compaction is applied to a functional test sequence from which functional broadside tests are extracted. The compact sequence yields a compact functional broadside test set. (2) Compaction of the functional test sequence is performed without sequential fault simulation. This is possible since test compaction does not have to preserve the fault coverage of the functional test sequence. The solution is developed in the scenario where the primary input vectors of a circuit are not constrained during functional operation. Experimental results for benchmark circuits demonstrate its ability to compact a functional broadside test set for transition faults.

[1]  Irith Pomeranz Generation of close-to-functional broadside tests with equal primary input vectors , 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[2]  Irith Pomeranz,et al.  Primary Input Vectors to Avoid in Random Test Sequences for Synchronous Sequential Circuits , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Hideo Fujiwara,et al.  Functional Constraints vs. Test Compression in Scan-Based Delay Testing , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[4]  Arnaud Virazel,et al.  Exploring the impact of functional test programs re-used for power-aware testing , 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[5]  Ilia Polian,et al.  Functional Constraints vs. Test Compression in Scan-Based Delay Testing , 2006 .

[6]  Sudhakar M. Reddy,et al.  At-speed scan test with low switching activity , 2010, 2010 28th VLSI Test Symposium (VTS).

[7]  D. M. H. Walker,et al.  Power supply noise control in pseudo functional test , 2013, 2013 IEEE 31st VLSI Test Symposium (VTS).

[8]  Irith Pomeranz,et al.  Generation of Functional Broadside Tests for Transition Faults , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[9]  Irith Pomeranz Close-to-Functional Broadside Tests With a Safety Margin , 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Irith Pomeranz Piecewise-Functional Broadside Tests Based on Reachable States , 2015, IEEE Transactions on Computers.

[11]  Irith Pomeranz,et al.  New Techniques to Reduce the Execution Time of Functional Test Programs , 2017, IEEE Transactions on Computers.

[12]  Irith Pomeranz,et al.  Definition and generation of partially-functional broadside tests , 2009, IET Comput. Digit. Tech..

[13]  Irith Pomeranz Scan Shift Power of Functional Broadside Tests , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[14]  Irith Pomeranz On the generation of scan-based test sets with reachable states for testing under functional operation conditions , 2004, Proceedings. 41st Design Automation Conference, 2004..

[15]  Feng Lu,et al.  Constraint extraction for pseudo-functional scan-based delay testing , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[16]  Irith Pomeranz,et al.  On generating pseudo-functional delay fault tests for scan designs , 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).

[17]  Jeff Rearick Too much delay fault coverage is a bad thing , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[18]  Irith Pomeranz Static test compaction procedure for large pools of multicycle functional broadside tests , 2018, IET Comput. Digit. Tech..

[19]  Irith Pomeranz,et al.  On static compaction of test sequences for synchronous sequential circuits , 1996, DAC '96.

[20]  Shlomi Sde-Paz,et al.  Frequency and Power Correlation between At-Speed Scan and Functional Tests , 2008, 2008 IEEE International Test Conference.

[21]  Kenneth M. Butler,et al.  A case study of ir-drop in structured at-speed testing , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[22]  Arnaud Virazel,et al.  A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing , 2011, 2011 Sixteenth IEEE European Test Symposium.