Algorithms for the automatic extension of an instruction-set

In this paper, two general algorithms for the automatic generation of instruction-set extensions are presented. The basic instruction set of a reconfigurable architecture is specialized with new application-specific instructions. The paper proposes two methods for the generation of convex multiple input multiple output instructions, under hardware resource constraints, based on a two-step clustering process. Initially, the application is partitioned in single-output instructions of variable size and then, selected clusters are combined in convex multiple output clusters following different policies. Our results on well-known kernels show that the extended instructions-set allows to execute applications more efficiently and needing fewer cycles. Our results show that a significant overall application speed-up is achieved even for large kernels (for ADPCM decoder the speed-up is up to x2.2 and for TWOFISH encoder the speedup is up to x5.5).

[1]  Srivaths Ravi,et al.  Synthesis of custom processors based on extensible platforms , 2002, ICCAD 2002.

[2]  Jonathan Rose,et al.  Area and delay trade-offs in the circuit and architecture design of FPGAs , 2008, FPGA '08.

[3]  Stamatis Vassiliadis,et al.  Automatic selection of application-specific instruction-set extensions , 2006, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06).

[4]  Tulika Mitra,et al.  Scalable custom instructions identification for instruction-set extensible processors , 2004, CASES '04.

[5]  Miodrag Potkonjak,et al.  MediaBench: a tool for evaluating and synthesizing multimedia and communications systems , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.

[6]  Paolo Ienne,et al.  Exploiting pipelining to relax register-file port constraints of instruction-set extensions , 2005, CASES '05.

[7]  Stamatis Vassiliadis,et al.  A Linear Complexity Algorithm for the Automatic Generation of Convex Multiple Input Multiple Output Instructions , 2007, ARC.

[8]  Nikil D. Dutt,et al.  ISEGEN: generation of high-quality instruction set extensions by iterative improvement , 2005, Design, Automation and Test in Europe.

[9]  Krzysztof Kuchcinski,et al.  Automatic Selection of Application-Specific Reconfigurable Processor Extensions , 2008, 2008 Design, Automation and Test in Europe.

[10]  Robert K. Brayton,et al.  HW/SW partitioning and code generation of embedded control applications on a reconfigurable architecture platform , 2002, Proceedings of the Tenth International Symposium on Hardware/Software Codesign. CODES 2002 (IEEE Cat. No.02TH8627).

[11]  Cesare Alippi,et al.  A DAG-Based Design Approach for Reconfigurable VLIW Processors , 1999, DATE.

[12]  Kingshuk Karuri,et al.  A design flow for configurable embedded processors based on optimized instruction set extension synthesis , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[13]  Stamatis Vassiliadis,et al.  DWARV: Delftworkbench Automated Reconfigurable VHDL Generator , 2007, 2007 International Conference on Field Programmable Logic and Applications.

[14]  Scott A. Mahlke,et al.  Processor Acceleration Through Automated Instruction Set Customization , 2003, MICRO.

[15]  Jason Cong,et al.  Application-specific instruction generation for configurable processor architectures , 2004, FPGA '04.

[16]  Stamatis Vassiliadis,et al.  The Spiral Search: A Linear Complexity Algorithm for the Generation of Convex MIMO Instruction-Set Extensions , 2007, 2007 International Conference on Field-Programmable Technology.

[17]  Paolo Ienne,et al.  Automatic application-specific instruction-set extensions under microarchitectural constraints , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[18]  Mahmut T. Kandemir,et al.  Switch Box Architectures for Three-Dimensional FPGAs , 2006, 2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

[19]  Tulika Mitra,et al.  Disjoint Pattern Enumeration for Custom Instructions Identification , 2007, 2007 International Conference on Field Programmable Logic and Applications.

[20]  Stamatis Vassiliadis,et al.  The MOLEN polymorphic processor , 2004, IEEE Transactions on Computers.

[21]  Koen Bertels,et al.  Automatic Instruction-Set Extensions with the Linear Complexity Spiral Search , 2008, 2008 International Conference on Reconfigurable Computing and FPGAs.

[22]  Günhan Dündar,et al.  An integer linear programming approach for identifying instruction-set extensions , 2005, 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05).

[23]  Stamatis Vassiliadis,et al.  A Linear Complexity Algorithm for the Generation of Multiple Input Single Output Instructions of Variable Size , 2007, SAMOS.

[24]  Majid Sarrafzadeh,et al.  Instruction generation for hybrid reconfigurable systems , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).