An ASIC design for the Ethernet-ATM Bridge

This paper presents the design and implementation of an ASIC of the Ethernet-ATM Bridge which is fabricated in UMC 0.18 μm 1P6M CMOS process. The main function of this chip is to build a bridge between Ethernet and ATM which is not only to merge three chips into a single chip, but also to give up the RISC processor. This development will enhance the broadband network switching ability and stability with small chip size and lower cost. The simulation results present that the gate number, the clock frequency, and the power consumption are 32 kilo-gates, 50 MHz, and 40.2 mW, respectively.