Semiconductor memory device and parallel bit test method thereof

A semiconductor memory device and a parallel bit test method thereof are provided to format expected data at free, by generating the expected data using a number of original expected data provided through an address pad. A memory cell array(10) includes a number of memory cells. An expected data generation part(70) generates a number of expected data, by using a number of original expected data provided through a number of address pads during read operation. A parallel bit test circuit(200) generates test result data, by comparing read data read out from the memory cells during the read operation with expected data provided from the expected data generation part.