esim: a structural design language and simulator for computer architecture education

We have developed a structural design language for use in undergraduate computer architecture classes that has much of the power of VHDL with little of the complexity. This language, esim, allows students to build arbitrarily complex digital logic designs using simple hierarchical design techniques. Students can simulate and debug their designs using a simulator implemented as a Tcl module. Because esim was not intended for designing and building physical circuits, it omits many of the primitives necessary for "real" hardware design and instead focuses on the concepts necessary for teaching students about digital designs. We have used esim as a teaching tool in undergraduate computer architecture classes at UMBC for several semesters. Students in these classes have implemented projects as complex as a pipelined RISC processor and a full 16x16 combinational multiplier. The compiler and simulator for the language are freely distributable, and may be expanded using standard Tcl packages and Tcl code. Current simulator modules include one for displaying signal values on the screen; modules that graph signal values are planned.