User- and process-driven dynamic voltage and frequency scaling

We describe and evaluate two new, independently-applicable power reduction techniques for power management on processors that support dynamic voltage and frequency scaling (DVFS): user-driven frequency scaling (UDFS) and process-driven voltage scaling (PDVS). In PDVS, a CPU-customized profile is derived offline that encodes the minimum voltage needed to achieve stability at each combination of CPU frequency and temperature. On a typical processor, PDVS reduces the voltage below the worst-case minimum operating voltages given in datasheets. UDFS, on the other hand, dynamically adapts CPU frequency to the individual user and the workload through direct user feedback. Our UDFS algorithms dramatically reduce typical operating frequencies and voltages while maintaining performance at a satisfactory level for each user. We evaluate our techniques independently and together through user studies conducted on a Pentium M laptop running Windows applications. We measure the overall system power and temperature reduction achieved by our methods. Combining PDVS and the best UDFS scheme reduces measured system power by 49.9% (27.8% PDVS, 22.1% UDFS), averaged across all our users and applications, compared to Windows XP DVFS. The average temperature of the CPU is decreased by 13.2°C. User trace-driven simulation to evaluate the CPU only indicates average CPU dynamic power savings of 57.3% (32.4% PDVS, 24.9% UDFS), with a maximum reduction of 83.4%. In a multitasking environment, the same UDFS+PDVS technique reduces the CPU dynamic power by 75.7% on average.

[1]  Niraj K. Jha,et al.  An energy-aware framework for coordinated dynamic software management in mobile computers , 2004, The IEEE Computer Society's 12th Annual International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems, 2004. (MASCOTS 2004). Proceedings..

[2]  Margaret Martonosi,et al.  A dynamic compilation framework for controlling microprocessor energy and performance , 2005, 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'05).

[3]  Peter A. Dinda,et al.  PICSEL: measuring user-perceived performance to control dynamic frequency scaling , 2008, ASPLOS.

[4]  James Tschanz,et al.  Parameter variations and impact on circuits and microarchitecture , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[5]  Chandra Krintz,et al.  AutoDVS: an automatic, general-purpose, dynamic clock scheduling system for hand-held devices , 2005, EMSOFT.

[6]  Peter A. Dinda,et al.  User-driven scheduling of interactive virtual machines , 2004, Fifth IEEE/ACM International Workshop on Grid Computing.

[7]  A. Waizman,et al.  Resonant free power network design using extended adaptive voltage positioning (EAVP) methodology , 2001 .

[8]  Rami G. Melhem,et al.  Minimizing expected energy in real-time embedded systems , 2005, EMSOFT.

[9]  Margaret Martonosi,et al.  Dynamic thermal management for high-performance microprocessors , 2001, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture.

[10]  Peter A. Dinda,et al.  Power to the people: Leveraging human physiological traits to control microprocessor frequency , 2008, 2008 41st IEEE/ACM International Symposium on Microarchitecture.

[11]  R. D. Valentine,et al.  The Intel Pentium M processor: Microarchitecture and performance , 2003 .

[12]  Peter A. Dinda,et al.  Measuring and understanding user comfort with resource borrowing , 2004, Proceedings. 13th IEEE International Symposium on High performance Distributed Computing, 2004..

[13]  B. Brock,et al.  Dynamic power management for embedded systems [SOC design] , 2003, IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings..

[14]  Peter A. Dinda,et al.  Human-driven optimization , 2007 .

[15]  Jon Crowcroft,et al.  Eliminating periodic packet losses in the 4.3-Tahoe BSD TCP congestion control algorithm , 1992, CCRV.

[16]  Jason Flinn,et al.  Self-Tuning Wireless Network Power Management , 2003, MobiCom '03.

[17]  Massoud Pedram,et al.  Dynamic voltage and frequency scaling based on workload decomposition , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

[18]  Niraj K. Jha,et al.  User-perceived latency driven voltage scaling for interactive applications , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[19]  George Theocharous,et al.  Machine Learning for Adaptive Power Management , 2006 .

[20]  S. Dhar,et al.  Closed-loop adaptive voltage scaling controller for standard-cell ASICs , 2002, Proceedings of the International Symposium on Low Power Electronics and Design.

[21]  Parthasarathy Ranganathan,et al.  Energy-aware user interfaces and energy-adaptive displays , 2006, Computer.

[22]  Krisztián Flautner,et al.  Vertigo: Automatic Performance-Setting for Linux , 2002, OSDI.

[23]  Christer Svensson,et al.  Trading speed for low power by choice of supply and threshold voltages , 1993 .

[24]  Pradip Bose,et al.  The case for lifetime reliability-aware microprocessors , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..

[25]  Peter A. Dinda,et al.  Learning and Leveraging the Relationship between Architecture-Level Measurements and Individual User Satisfaction , 2008, 2008 International Symposium on Computer Architecture.

[26]  Erven Rohou,et al.  Dynamically Managing Processor Temperature and Power , 1999 .

[27]  Alan Jay Smith,et al.  Using user interface event information in dynamic voltage scaling algorithms , 2002, 11th IEEE/ACM International Symposium on Modeling, Analysis and Simulation of Computer Telecommunications Systems, 2003. MASCOTS 2003..

[28]  Avi Mendelson,et al.  On Estimating Optimal Performance of CPU Dynamic Thermal Management , 2003, IEEE Computer Architecture Letters.

[29]  Trevor Mudge,et al.  Vertigo: automatic performance-setting for Linux , 2002, OPSR.

[30]  Peter A. Dinda,et al.  Power reduction through measurement and modeling of users and CPUs: summary , 2007, SIGMETRICS '07.

[31]  Kevin Skadron,et al.  Temperature-aware microarchitecture: Modeling and implementation , 2004, TACO.

[32]  Sally Floyd,et al.  Simulation-based comparisons of Tahoe, Reno and SACK TCP , 1996, CCRV.

[33]  Trevor Mudge,et al.  Razor: a low-power pipeline based on circuit-level timing speculation , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..

[34]  Larry L. Peterson,et al.  TCP Vegas: new techniques for congestion detection and avoidance , 1994 .

[35]  Josep Torrellas,et al.  Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors , 2008, 2008 International Symposium on Computer Architecture.

[36]  Bishop Brock,et al.  Dynamic Power Management for Embedded Systems , 2003 .

[37]  Larry Peterson,et al.  TCP Vegas: new techniques for congestion detection and avoidance , 1994, SIGCOMM 1994.

[38]  W. Richard Stevens,et al.  TCP Slow Start, Congestion Avoidance, Fast Retransmit, and Fast Recovery Algorithms , 1997, RFC.

[39]  David Blaauw,et al.  Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation , 2003, MICRO.