DFT Computation Using Gauss-Eisenstein Basis: FFT Algorithms and VLSI Architectures

A joint numerical representation based on both Gaussian and Eisenstein integers is proposed. This Gauss-Eisenstein representation maps complex numbers into four-tuples of integers with arbitrarily high precision. The representation furnishes the computation of the 3-, 6-, and 12-point discrete Fourier transform (DFT) at any desired accuracy. The associated fast algorithms based on the Gauss-Eisenstein integers are error-free up to the final reconstruction step, which can be realized in hardware as a multiplierless implementation. The introduced methods are compared with competing algorithms in terms of arithmetic complexity. We propose three FRS architectures based on the following methods: Dempster-McLeod representation, expansion factor, and addition aware quantization. The Gauss-Eisenstein 12-point DFT is physically realized on a Xilinx Virtex 6 FPGA device with maximum clock frequency of 302 MHz for the expansion factor FRS with real-time throughput of <inline-formula><tex-math notation="LaTeX">$3.62\times 10^9$ </tex-math><alternatives><inline-graphic xlink:href="cintra-ieq1-2677427.gif"/></alternatives></inline-formula> coefficients/s. The FPGA verified digital designs were synthesized, mapped, placed and finally routed for <inline-formula><tex-math notation="LaTeX">$0.18\mu$</tex-math><alternatives> <inline-graphic xlink:href="cintra-ieq2-2677427.gif"/></alternatives></inline-formula>m CMOS technology assuming a 1.8 V DC supply employing Austria Micro Systems (AMS) standard-cell library (hitkit version 4.11). The routed ASIC is predicted to operate at a maximum frequency of 505 MHz for the expansion factor FRS with potential real-time throughput of <inline-formula><tex-math notation="LaTeX">$6.06\times 10^9$</tex-math><alternatives> <inline-graphic xlink:href="cintra-ieq3-2677427.gif"/></alternatives></inline-formula> coefficients/s.

[1]  G. Hardy,et al.  An Introduction to the Theory of Numbers , 1938 .

[2]  Harvey F. Silverman,et al.  An introduction to programming the Winograd Fourier transform algorithm (WFTA) , 1977 .

[3]  Anastasios N. Venetsanopoulos,et al.  The generalized discrete Fourier transform in rings of algebraic integers , 1980 .

[4]  S. Prakash,et al.  A new radix-6 FFT algorithm , 1981 .

[5]  John H. Cozzens,et al.  Computing the discrete Fourier transform using residue number systems in a ring of algebraic integers , 1985, IEEE Trans. Inf. Theory.

[6]  Richard E. Blahut,et al.  Fast Algorithms for Digital Signal Processing , 1985 .

[7]  Ken'iti Kido,et al.  A new FFT algorithm of radix 3, 6, and 12 , 1986, IEEE Trans. Acoust. Speech Signal Process..

[8]  Henrique S. Malvar.  Fast computation of discrete cosine transform through fast Hartley transform , 1986 .

[9]  John H. Cozzens,et al.  Range and error analysis for a fast Fourier transform computed over Z[{omega}] , 1987, IEEE Trans. Inf. Theory.

[10]  Hong Xin Huang,et al.  Fast parallel complex discrete fourier transforms using a multichannel optical correlator , 1988 .

[11]  S. White.  A radix-12 FFT building block , 1993, Proceedings of 27th Asilomar Conference on Signals, Systems and Computers.

[12]  I. D. Lu,et al.  Use of mixed radix FFT in electric power system studies , 1994 .

[13]  A. Dempster,et al.  Multiplication by an integer using minimum adders , 1994 .

[14]  A. Dempster,et al.  Constant integer multiplication using minimum adders , 1994 .

[15]  Graham A. Jullien,et al.  Eisenstein residue number system with applications to DSP , 1997, Proceedings of 40th Midwest Symposium on Circuits and Systems. Dedicated to the Memory of Professor Mac Van Valkenburg.

[16]  Graham A. Jullien,et al.  A residue number system implementation of real orthogonal transforms , 1998, IEEE Trans. Signal Process..

[17]  Jamal T. Manassah.  Elementary Mathematical and Computational Tools for Electrical and Computer Engineers Using MATLAB , 2001 .

[18]  Lin Yang,et al.  Design of a 3780-point IFFT processor for TDS-OFDM , 2002, IEEE Trans. Broadcast..

[19]  An-Yeu Wu,et al.  VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-Based Communication Systems , 2003, EURASIP J. Adv. Signal Process..

[20]  U. Jagdhold,et al.  A 64-point Fourier transform chip for high-speed wireless LAN application using OFDM , 2004, IEEE Journal of Solid-State Circuits.

[21]  Gerlind Plonka,et al.  A global method for invertible integer DCT and integer wavelet algorithms , 2004 .

[22]  Shmuel Winograd.  Some bilinear forms whose multiplicative complexity depends on the field of constants , 2005, Mathematical systems theory.

[23]  Kiran George,et al.  Design and performance evaluation of a 2.5-GSPS digital receiver , 2005, IEEE Transactions on Instrumentation and Measurement.

[24]  P.K. Meher,et al.  A New Convolutional Formulation of the DFT and Efficient Systolic Implementation , 2005, TENCON 2005 - 2005 IEEE Region 10 Conference.

[25]  Jamal T. Manassah.  Elementary Mathematical and Computational Tools for Electrical and Computer Engineers Using Matlab, Second Edition , 2006 .

[26]  A NikaraJari,et al.  Discrete cosine and sine transforms , 2006 .

[27]  Vladimir Britanak,et al.  CHAPTER 1 – Discrete Cosine and Sine Transforms , 2006 .

[28]  Jean-Christophe Prévotet,et al.  Implementation of a reconfigurable Fast Fourier Transform application to digital terrestrial television broadcasting , 2009, 2009 International Conference on Field Programmable Logic and Applications.

[29]  Oscar Gustafsson,et al.  Addition Aware Quantization for Low Complexity and High Precision Constant Multiplication , 2010, IEEE Signal Processing Letters.

[30]  Richard E. Blahut,et al.  Fast Algorithms for Signal Processing: Acknowledgments , 2010 .

[31]  Rui Lv,et al.  A novel 3780-point FFT , 2010, 2010 IEEE International Conference on Wireless Communications, Networking and Information Security.

[32]  Pramod Kumar Meher.  Memory-Based Computation of Inner-Product for Digital Signal Processing Applications , 2010, 2010 International Symposium on Electronic System Design.

[33]  Peter Nilsson,et al.  On hardware implementation of radix 3 and radix 5 FFT kernels for LTE systems , 2011, 2011 NORCHIP.

[34]  Pei-Yun Tsai,et al.  Automatic IP Generation of FFT/IFFT Processors with Word-Length Optimization for MIMO-OFDM Systems , 2011, EURASIP J. Adv. Signal Process..

[35]  Yun Chen,et al.  A multi-core mapping implementation of 3780-point FFT , 2012, 2012 International SoC Design Conference (ISOCC).

[36]  Arjuna Madanayake,et al.  A Row-Parallel 8$\,\times\,$ 8 2-D DCT Architecture Using Algebraic Integer-Based Exact Computation , 2012, IEEE Transactions on Circuits and Systems for Video Technology.

[37]  Vassil S. Dimitrov,et al.  Representação Numérica em Inteiros de Gauss-Eisenstein , 2012 .

[38]  Luca Fanucci,et al.  Design and Comparison of FFT VLSI Architectures for SoC Telecom Applications with Different Flexibility, Speed and Complexity Trade-Offs , 2012, Circuits Syst. Signal Process..

[39]  Zhiyi Yu,et al.  Efficient implementation of 3780-point FFT on a 16-core processor , 2013, 2013 IEEE 10th International Conference on ASIC.

[40]  Oscar Gustafsson,et al.  Unified architecture for 2, 3, 4, 5, and 7-point DFTs based on Winograd Fourier transform algorithm , 2013 .

[41]  Arjuna Madanayake,et al.  VLSI Architectures for the 4-Tap and 6-Tap 2-D Daubechies Wavelet Filters Using Algebraic Integers , 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

[42]  Arjuna Madanayake,et al.  Precise VLSI Architecture for AI Based 1-D/ 2-D Daub-6 Wavelet Filter Banks With Low Adder-Count , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

[43]  Shikha Tripathi,et al.  Systolic architecture implementation of 1D DFT and 1D DCT , 2015, 2015 IEEE International Conference on Signal Processing, Informatics, Communication and Energy Systems (SPICES).

[44]  Susana Ortega Cisneros,et al.  FPGA design and implementation of radix-2 Fast Fourier Transform algorithm with 16 and 32 points , 2015 .

[45]  Yasuhiko Nakashima,et al.  ASIC design of MUL-RED Radix-2 Pipeline FFT circuit for 802.11ah system , 2016, 2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX).