A Contribution to the Discrete Z-Domain Analysis of ADPLL

In this paper, a new z-domain model for all-digital phase-locked loop (ADPLL) whose output frequency is inversely proportional to the control word of digital controlled oscillator (DCO) is proposed. With this new z-domain model, bandwidth and phase margin can still be acquired for these ADPLLs. Finally, a cycle-domain simulator is written to verify the correctness of z-domain model and the results are in good agreement within only 0.3-db measurement error bars.

[1]  Pavan Kumar Hanumolu,et al.  A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

[2]  P. Nilsson,et al.  A digitally controlled PLL for SoC applications , 2004, IEEE Journal of Solid-State Circuits.

[3]  Poras T. Balsara,et al.  Phase-domain all-digital phase-locked loop , 2005, IEEE Transactions on Circuits and Systems II: Express Briefs.

[4]  Ching-Che Chung,et al.  A portable digitally controlled oscillator using novel varactors , 2005, IEEE Trans. Circuits Syst. II Express Briefs.

[5]  Roland E. Best.  Phase-locked loops : design, simulation, and applications , 2003 .

[6]  F. Gardner,et al.  Charge-Pump Phase-Lock Loops , 1980, IEEE Trans. Commun..

[7]  J. W. Scott,et al.  z-domain model for discrete-time PLL's , 1988 .