동적으로 듀티사이클이 변하는 입력 클럭에도 일정한 듀티사이클 출력을 갖는 지연동기루프의 설계

This paper proposes a delay-locked loop (DLL) that supports stable operation even if the duty-cycle of the input clock varies dynamically. It reconstructs the clock from the rising edge of the input clock and operates with the clock of which the duty-cycle ranges from 20% to 80%. The prototype chip was implemented in a 0.13㎛ CMOS process and occupies an area of 0.03㎟. It operates from 200㎒ to 700㎒ and consumes a power of 6㎽ at 500㎒.