High throughput and low area architectures of secure IoT algorithm for medical image encryption

Abstract The favor that lightweight encryption algorithms have gained over the recent years regarding data and image security in a resource constrained environment of the smart device sort in Internet of Things (IoT) is undeniable. Secure IoT (SIT) is a popular encryption algorithm that tends to consume less hardware resources due to simple operation, which serves a welcome advantage, since it is precisely the reduction of area and power consumption. In this paper, high-speed and low-area architectures are proposed for SIT algorithm under resource constrained applications. The proposed pipelined architecture is useful in high frequency applications, and proposed serial architecture is useful for low area requirement, leads to reduce the cost incurred on hardware. The proposed design can support four different block sizes of an input medical ultrasonic image, namely 32  ×  32, 64  ×  64, 128  ×  128 and 256  ×  256 along with Finite State Machine (FSM) controller. The dynamic size of block selection technique saves significant amount of clock cycles during image encryption. The proposed designs have implemented in FPGA XC5VLX50T-3ff1136 device and achieved maximum operating frequency of 287.51 MHz in pipelined architecture and number of slices 46 in serial architecture. PRESENT is an efficient lightweight block cipher having 73 slices in serial architecture whereas proposed serial architecture provides 58.69% improvement in area. LEA is a popular Feistel block cipher generates maximum frequency of 217 MHz in pipelined architecture, but at the same time proposed pipelined architecture provides 32.25% enhancement in speed.