A resistive DAC for a multi-stage sigma-delta modulator DAC with dynamic element matching

This paper presents a study and implementation of a shunt–shunt resistive voltage divider digital-to-analog converter (DAC) for use as a multibit DAC in a multi-stage noise shaping sigma-delta modulator DAC design with dynamic element matching. This resistive DAC structure is employed to address the problem of code-dependent finite output impedance and thus aims to improve systematic linearity, while still being suitable for scaled CMOS processes. Chip measurement results from an implementation in CMOS 180 nm technology are presented. At low sampling clock frequencies, an SFDR of 71.81 dB is achieved, while at a higher sampling clock frequency of 600 MHz the SFDR is measured to be 59.73 dB, all for an OSR of 32. Our results show that low systematic nonlinearity can be achieved with this resistive DAC at low sampling frequencies, and we discuss potential enhancements to our prototype to obtain better SFDR at higher sampling rate.

[1]  Martin Clara,et al.  High-Performance D/A-Converters: Application to Digital Transceivers , 2012 .

[2]  Mounir Fares,et al.  Digital Approaches to ISI-Mitigation in High-Resolution Oversampled Multi-Level D/A Converters , 2011, IEEE Journal of Solid-State Circuits.

[3]  Shanthi Pavan,et al.  Design Techniques for Wideband Single-Bit Continuous-Time $\Delta\Sigma$ Modulators With FIR Feedback DACs , 2012, IEEE Journal of Solid-State Circuits.

[4]  An 11 GS/s 1.1 GHz Bandwidth Interleaved ΔΣ DAC for 60 GHz Radio in 65 nm CMOS , 2015, IEEE Journal of Solid-State Circuits.

[5]  W. Guggenbuhl,et al.  A high-swing, high-impedance MOS cascode circuit , 1990 .

[6]  Trond Ytterdal,et al.  Analog Circuit Design in Nanoscale CMOS Technologies , 2009, Proceedings of the IEEE.

[7]  Tai-Haur Kuo,et al.  An improved technique for reducing baseband tones in sigma-delta modulators employing data weighted averaging algorithm without adding dither , 1999 .

[8]  Yintang Yang,et al.  A 2nd-order sigma-delta mismatch-shaping current-steering DAC for zigbee transmitters , 2014 .

[9]  T.S. Fiez,et al.  A 14-bit current-mode /spl Sigma//spl Delta/ DAC based upon rotated data weighted averaging , 2000, IEEE Journal of Solid-State Circuits.

[10]  Nan Sun,et al.  Dynamic Element Matching With Signal-Independent Element Transition Rates for Multibit $\Delta\Sigma$ Modulators , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

[11]  Gabor C. Temes,et al.  A 0.8 V, 2.6 mW, 88 dB Dual-Channel Audio Delta-Sigma D/A Converter With Headphone Driver , 2009, IEEE Journal of Solid-State Circuits.

[12]  Atsushi Iwata,et al.  VLSI- A to D and D to A converters with multi-stage noise shaping modulators , 1986, ICASSP '86. IEEE International Conference on Acoustics, Speech, and Signal Processing.

[13]  Hae-Seung Lee,et al.  Output impedance requirements for DACs , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[14]  Qiuting Huang,et al.  A 13-b 1.1-MHz oversampled DAC with semidigital reconstruction filtering , 2004, IEEE Journal of Solid-State Circuits.

[15]  Zoya Popovic,et al.  Circuit Approaches to Nonlinear-ISI Mitigation in Noise-Shaped Bandpass D/A Conversion , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[16]  Douglas Mercer.  A study of error sources in current steering digital-to-analog converters , 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).

[17]  Torsten Lehmann,et al.  Design strategy for enhanced output impedance current-steering DAC in sigma-delta converters , 2013, 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS).

[18]  Atsushi Iwata,et al.  A 17 bit oversampling D-A conversion technology using multistage noise shaping , 1989 .

[19]  Nan Sun,et al.  A random DEM technique with minimal element transition rate for high-speed DACs , 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

[20]  Oliver M. Collins,et al.  Measurement and Reduction of ISI in High-Dynamic-Range 1-bit Signal Generation , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[21]  A. Wiesbauer,et al.  A 350MHz low-OSR /spl Delta//spl Sigma/ current-steering DAC with active termination in 0.13 /spl mu/m CMOS , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[22]  B. Miller,et al.  A multiple modulator fractional divider , 1991 .

[23]  Michael C. W. Coln,et al.  A 20b clockless DAC with sub-ppm-linearity 7.5nV/vHz-noise and 0.05ppm/°C-stability , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[24]  Gabor C. Temes,et al.  Understanding Delta-Sigma Data Converters , 2004 .