Synchronous Digital Hierarchy Network Pointer Simulation

Abstract Pointer activity in Synchronous Transport Module 1 (STM1) networks is presented based on simulated models of various STM1 network configurations. The effects of clock stability, number of nodes, and First In First Out (FIFO) buffer sizes on pointer activity is included. Plesiochronous port mapping and demapping clocks are examined to determine plesiochronous port boundary clocking requirements. Loss of synchronization at gateway nodes is included to demonstrate the downstream impacts of network synchronization failures. Traditional pointer activity studies have been done on a behavioral basis, minimizing byte-by-byte calculations to reduce simulation time and resolution of results. This study approaches the problem from a different direction by using byte-by-byte calculations to determine, with more accuracy, pointer generation and interactions. Anticipated pointer activity is not easily obtained from analysis of STM networks, instead simulation is required to obtain detailed information required to characterize pointer activity. The results of this paper are the expected nature of pointer activity in STM networks.