Development of a Place and Route Tool for the RaPiD Architecture

In recent years, designers have begun to migrate to the System-on-a-Chip (SOC) paradigm from traditional board-level design methods. New fabrication technologies have enabled the production of integrated circuits that have hundreds of millions of transistors. This capability has motivated the VLSI design community to investigate the possibility of integrating the subsystems that comprise a traditional board-level design on a single piece of silicon. There are several important reasons for moving to SOC. Significant factors include increased inter-device communication bandwidth, reduced power consumption, and overall area improvement. However, there are challenges that need to be addressed. SOCs typically have a very large design space, thus complicating existing tool-flows. Interfacing the individual subsystems on the chip is another major issue. There is also a considerable increase in prototyping costs due to the size of the final design. Finally, there is a lack of post-fabrication flexibility. This is because designers can easily remove and replace components in board designs, a feature that is noticeably absent in present day SOC. Designing an SOC targeted to a single application could prove extremely expensive if the hardware requirements of the application vary with time. It is therefore clear that a reconfigurable subsystem would be useful in SOC. This reconfigurable subsystem would provide the desired hardware flexibility to SOC designs. The immediate solution to lack of post-fabrication flexibility of SOC designs is to include a Field Programmable Gate Array (FPGA) core designed by a major commercial vendor. However, current FPGA architectures fall considerably short of the levels of performance that can be expected from Application Specific Integrated Circuit (ASIC) implementations. This is because FPGAs aim to provide a great deal of flexibility in hardware, resulting in a performance trade-off. 3 Domain-specific reconfigurable architectures attempt to bridge the wide gap in performance that exists between ASICs and FPGAs. Such architectures are targeted to specific application domains (Digital Signal Processing (DSP), for example), and contain customized computational elements that are optimized to perform functions that fall within that domain. RaPiD[4,6] and PipeRench[7] are examples of domain-specific reconfigurable architectures. The computational elements in these architectures can be configured to execute a variety of DSP applications. Thus, if an SOC were to be designed for a predetermined domain of applications, the corresponding domain-specific architecture would form the reconfigurable core. In this way, near-ASIC performance levels could be achieved, while providing hardware flexibility attributed to commercial FPGAs. While domain-specific architectures are an …