8 – Structural Levels of the PDP-8

Publisher Summary This chapter focuses on the structural levels of PDP-8 and presents a map of the PDP-8 design hierarchy, starting from the processor-memory-switch structure to the instruction set processor (ISP), and down through logic design to circuit electronics. These description levels are subdivided to provide more organizational details such as registers, data operators, and functional units at the register transfer level. The relationship of the various description levels constitutes a tree structure, where the organizationally complex computer is the top node and each descending description level represents increasing detail until the final circuit element level is reached. The ISP of the PDP-8 processor is the simplest for a general purpose stored program computer. It operates on 12-bit words, 12-bit integers, and 12-bit Boolean vectors. The chapter highlights the combinational logic elements used in the PDP-8. The circuit selection is limited to the inverter circuit with single or multiple inputs. These are more familiarly called NAND gates or NOR gates, depending on whether positive and/or negative logic level definitions are used.