A Dedicated Reconfigurable Architecture for Finite State Machines

For ultra-low-power sensor networks, finite state machines are used for simple tasks where the system’s microprocessor would be overqualified. This allows the microprocessor to remain in a sleep state, thus saving energy. This paper presents a new architecture that is specifically optimized for implementing reconfigurable Finite State Machines: Transition-based Reconfigurable FSM (TR-FSM). The proposed architecture combines low use of resources with a (nearly) FPGA-like reconfigurability.

[1]  G. Palumbo,et al.  Interconnect-Aware Design of Fast Large Fan-In CMOS Multiplexers , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

[2]  Ming-Bo Lin,et al.  On the design of fast large fan-in CMOS multiplexers , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Randy H. Katz,et al.  Contemporary Logic Design , 2004 .

[4]  Wim Vanderbauwhede,et al.  Implementation of Finite State Machines on a Reconfigurable Device , 2007, Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007).

[5]  Reiner W. Hartenstein,et al.  Coarse grain reconfigurable architecture (embedded tutorial) , 2001, ASP-DAC '01.

[6]  T. Arslan,et al.  A high performance synthesisable unsymmetrical reconfigurable fabric for heterogeneous finite state machines , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[7]  Arkadiusz Bukowiec,et al.  SYNTHESIS OF FINITE STATE MACHINES FOR PROGRAMMABLE DEVICES BASED ON MULTI-LEVEL IMPLEMENTATION , 2008 .

[8]  Reiner W. Hartenstein.  Coarse grain reconfigurable architectures , 2001, Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455).

[9]  Jan M. Rabaey,et al.  Digital Integrated Circuits , 2003 .

[10]  I. Xilinx.  Virtex series configuration architecture user guide , 2000 .