Investigation of Area-Timing Trade off for Merged Delay Transformed Interpolator

Interpolator is widely used signal processing component and it is used to increase the sampling rate of input signal. It finds applications in communication transmitters, digital audio systems, digital analog conversion systems and digital image processing systems to gain specific performance advantages. The process of interpolation consists of two steps. First is the up sampling or zero insertion process that is followed by the low pass filtering process. The low pass filtering assigns suitable values to the inserted zero valued samples or in frequency domain removes the image frequencies created by the up-sampling process. In the traditional interpolators using recursive filters these two operations are performed separately. The quest for finding computationally efficient multi rate filter architectures has triggered a lot of research work. A variety of filter architectures have been proposed each having their own advantages and disadvantages. A new transformation has recently been proposed under the name of Merged Delay Transformation that transforms the architecture of the recursive filter. The advantage of Merged Delay Transformed filter is that it provides a mechanism to combine the two processes in a single unit in computationally efficient way. Efficient hardware implementation of an Interpolator based on Merged Delay Transformation is focused in this paper. A typical design problem of a CD player Digital Analog Conversion interpolation filter is selected. Merged Delay Transformed interpolation filter, standard recursive filter architecture as a cascade of second order sections and polyphase decomposed FIR implementation are passed through the implementation steps constrained under the specifications imposed by the design problem. The paper will focus on area timing trade off using different schemes for MDT implementation on FPGA.