Competitive learning: what are the circuit limitations?

This paper examines issues relating to analog CMOS circuit implementation of the soft competitive neural learning algorithm. Simulations of a proposed implementation have been conducted based on hardware models constructed from actual measurements of 1.2 /spl mu/m CMOS analog components, primarily (nonlinear) Gilbert multipliers and associated circuits. We have used these same components in the past to construct hardware versions of contrastive Hebbian learning and delta learning. The chips with contrastive Hebbian learning have been tested and observed to perform correctly on associative learning tasks. In the present study, simulations using these same empirical hardware models demonstrate that a generalized version of the soft competitive learning algorithm is capable of discovering appropriate features in an unsupervised learning mode. It has also been found that an in-circuit version of the soft competitive learning algorithm is well suited to fabrication in analog CMOS circuitry. Inherent fabrication variations, such as transistor threshold variation and circuit noise, do not significantly impact the performance of the algorithm on a selected test problem. Multiplier zero crossing offsets were Initially found to greatly degrade network performance, but this effect was overcome by imposing minimum thresholds on weight updates, which require the addition of a small amount of thresholding circuitry.