On Detailed Routing for a Hierarchical Scalable Recon gurable Array With Constrained Switching Capability CS-270 Course Project

In modern FPGA CAD ow, netlist routing on a particular routing architecture is solved in two steps, global routing based on wire bandwidth constraints of the architecture, and subsequent detailed routing based on the ner switching constraints of the architecture. Detailed routing is dif-cult and provably NP-complete in popular 2-D mesh architectures such as the Xilinx 4000 series FPGAs 16]. Certain tree based routing architec-tures, which are desirable for scalability and area universality 11], have known polynomial algorithms and guarantees for detailed routing. In this paper we study approaches to detailed routing for a fat-tree routing architecture with restricted switching topology, in which routing bandwidth scales according to Rent's Rule. We discuss several formulations and frameworks for solving the detailed routing problem, using such techniques as graph coloring, multicomodity ow, and integer linear programming.

[1]  H. James Hoover,et al.  Bounding Fan-out in Logical Networks , 1984, JACM.

[2]  Fanica Gavril,et al.  Algorithms for Minimum Coloring, Maximum Clique, Minimum Covering by Cliques, and Maximum Independent Set of a Chordal Graph , 1972, SIAM J. Comput..

[3]  Charles E. Leiserson,et al.  VLSI theory and parallel supercomputing , 1989 .

[4]  A. Mullin,et al.  Mathematical Theory of Connecting Networks and Telephone Traffic. , 1966 .

[5]  Fillia Makedon,et al.  Fast Approximation Algorithms for Multicommodity Flow Problems , 1995, J. Comput. Syst. Sci..

[6]  R. Möhring.  Algorithmic graph theory and perfect graphs , 1986 .

[7]  Malgorzata Marek-Sadowska,et al.  Graph based analysis of 2-D FPGA routing , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  F. Leighton,et al.  Introduction to Parallel Algorithms and Architectures: Arrays, Trees, Hypercubes , 1991 .

[9]  Ronald I. Greenberg,et al.  The Fat-Pyramid and Universal Parallel Computation Independent of Wire Delay , 1994, IEEE Trans. Computers.

[10]  M. Golummc.  Algorithmic graph theory and perfect graphs , 1980 .

[11]  Sadiq M. Sait,et al.  VLSI Physical Design Automation - Theory and Practice , 1995, Lecture Notes Series on Computing.

[12]  Tommy R. Jensen,et al.  Graph Coloring Problems , 1994 .

[13]  Charles E. Leiserson,et al.  Fat-trees: Universal networks for hardware-efficient supercomputing , 1985, IEEE Transactions on Computers.

[14]  Steven Skiena,et al.  The Algorithm Design Manual , 2020, Texts in Computer Science.

[15]  V. G. Vizing.  The chromatic class of a multigraph , 1965 .

[16]  Bhawani Sankar Panda,et al.  New Linear Time Algorithms for Generating Perfect Elimination Orderings of Chordal Graphs , 1996, Inf. Process. Lett..

[17]  Frank Thomson Leighton.  Introduction to parallel algorithms and architectures: arrays , 1992 .

[18]  Philip N. Klein,et al.  Faster Approximation Algorithms for the Unit Capacity Concurrent Flow Problem with Applications to Routing and Finding Sparse Cuts , 1994, SIAM J. Comput..