Read and Pass Disturbance in the Programmed States of Floating Gate Flash Memory Cells With High-$\kappa$ Interpoly Gate Dielectric Stacks

High-κ stacks have been used in the 20-nm generation of floating gate (FG) flash memory cells as the interpoly dielectric (IPD). However, electron trapping in high-κ materials remains a major concern for the further development of FG technology. For conventional FG cells, read/pass disturbance in the erased states is a major issue. In this paper, for the first time, it is observed that electron trapping/detrapping in the high-κ IPD layers can cause severe abnormal read/pass disturbances in the programmed states. Extensive evidence shows that this instability in programmed states originates from several competing mechanisms, including the redistribution of electron trapping between the IPD and FG and the electron discharging from FG/IPD into the control gate. This issue should be addressed in the development of future generations of FG Flash technology with higher-κ IPD materials.

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