An Advanced BIRA for Memories With an Optimal Repair Rate and Fast Analysis Speed by Using a Branch Analyzer

As memory capacity and density grow, a corresponding increase in the number of defects decreases the yield and quality of embedded memories for systems-on-chip as well as commodity memories. For embedded memories, built-in redundancy analysis (BIRA) is widely used to solve quality and yield issues by replacing faulty cells with healthy redundant cells. Many BIRA approaches require extra hardware overhead in order to achieve optimal repair rates, or they suffer a loss of repair rate in minimizing the hardware overhead. An innovative BIRA approach is proposed to achieve optimal repair rates, lower area overhead, and increase analysis speed. The proposed BIRA minimizes area overhead by eliminating some storage coverage for only must-repair faulty information. The proposed BIRA analyzes redundancies quickly and efficiently by evaluating all nodes of a branch in parallel with a new analyzer which is simple and easy-to-implement. Experimental results show that the proposed BIRA allows for a much faster analysis speed than that of the state-of-the-art BIRA, as well as the optimal repair rate, and relatively small area overhead.

[1]  Hung-Yau Lin,et al.  An efficient algorithm for spare allocation problems , 2006, IEEE Transactions on Reliability.

[2]  Shyue-Kung Lu,et al.  Efficient BISR Techniques for Word-Oriented Embedded Memories with Hierarchical Redundancy , 2006, 5th IEEE/ACIS International Conference on Computer and Information Science and 1st IEEE/ACIS International Workshop on Component-Based Software Engineering,Software Architecture and Reuse (ICIS-COMSAR'06).

[3]  Sungho Kang,et al.  A Fast Built-in Redundancy Analysis for Memories With Optimal Repair Rate Using a Line-Based Search Tree , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  Shyue-Kung Lu,et al.  Efficient built-in redundancy analysis for embedded memories with 2-D redundancy , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  Cheng-Wen Wu,et al.  Economic Aspects of Memory Built-in Self-Repair , 2007, IEEE Design & Test of Computers.

[6]  O. Wada,et al.  Post-packaging auto repair techniques for fast row cycle embedded DRAM , 2004 .

[7]  Swapnil Bahl.  A Sharable Built-in Self-repair for Semiconductor Memories with 2-D Redundancy Scheme , 2007, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007).

[8]  Atsushi Nakayama,et al.  Post-packaging auto repair techniques for fast row cycle embedded DRAM , 2004, 2004 International Conferce on Test.

[9]  W. Kent Fuchs,et al.  Efficient Spare Allocation in Reconfigurable Arrays , 1986, 23rd ACM/IEEE Design Automation Conference.

[10]  Shyue-Kung Lu,et al.  A BIRA algorithm for embedded memories with 2D redundancy , 2005, 2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'05).

[11]  Yu-Jen Huang,et al.  A Built-In Redundancy-Analysis Scheme for Self-Repairable RAMs with Two-Level Redundancy , 2006, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[12]  Jin-Fu Li,et al.  A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[13]  Jin-Fu Li,et al.  Built-in redundancy analysis for memory yield improvement , 2003, IEEE Trans. Reliab..

[14]  Hans-Joachim Wunderlich,et al.  An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy , 2007, 12th IEEE European Test Symposium (ETS'07).

[15]  John Day.  A Fault-Driven, Comprehensive Redundancy Algorithm , 1985, IEEE Design & Test of Computers.

[16]  Jin-Fu Li,et al.  ReBISR: A Reconfigurable Built-In Self-Repair Scheme for Random Access Memories in SOCs , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[17]  Fabrizio Lombardi,et al.  New approaches for the repairs of memories with redundancy by row/column deletion for yield enhancement , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[18]  Hideto Hidaka,et al.  A built-in self-repair analyzer (CRESTA) for embedded DRAMs , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[19]  Jin-Fu Li,et al.  A Reconfigurable Built-In Self-Repair Scheme for Multiple Repairable RAMs in SOCs , 2006, 2006 IEEE International Test Conference.

[20]  D. M. Blough.  Performance evaluation of a reconfiguration-algorithm for memory arrays containing clustered faults , 1996, IEEE Trans. Reliab..

[21]  C.L. Liu,et al.  Fast search algorithms for reconfiguration problems , 1991, [Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems.

[22]  K. Pagiamtzis,et al.  Content-addressable memory (CAM) circuits and architectures: a tutorial and survey , 2006, IEEE Journal of Solid-State Circuits.